68HC05PL4 Datasheet, PDF (42/98 Pages) Freescale Semiconductor, Inc – Industry standard 8-bit M68HC05 CPU core

Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
April 30, 1998
6.2 LOW POWER MODES
In each of its con gur ation modes the MC68HC05PL4 is capable of running in one
of two low-power operating modes. The WAIT and STOP instructions provide two
modes that reduce the power required for the MCU by stopping various internal
clocks and/or the oscillator. The o w of the STOP, and WAIT modes are shown in
Figure 6-1.
6.2.1 STOP Mode
Execution of the STOP instruction places the MCU in its lowest power
consumption mode.
The MCU can exit from the STOP by an IRQ or Keyboard interrupt (KBIx), or an
externally generated RESET. When exiting the STOP mode the internal oscillator
will resume after 4064 internal processor clock cycles oscillator stabilization delay.
6.2.2 WAIT Mode
The WAIT instruction places the MCU in a low-power mode, which consumes
more power than the STOP Mode.
The WAIT mode may be exited by an external IRQ, a keyboard interrupt, 16-bit
timer interrupt, 8-bit timer interrupt, or by an external RESET.
OPERATING MODES
MC68HC05PL4
6-2
REV 2.0
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