MCF5329 Datasheet, PDF (40/50 Pages) Freescale Semiconductor, Inc – Microprocessor Data Sheet

Electrical Characteristics
QS1
QSPI_CS[3:0]
QSPI_CLK
QS2
QSPI_DOUT
QS3
QS4
QS5
QSPI_DIN
Figure 27. QSPI Timing
5.18 JTAG and Boundary Scan Timing
Table 29. JTAG and Boundary Scan Timing
Num
Characteristics¹
Symbol
Min
Max
J1 TCLK Frequency of Operation
f_JCYC
DC
1/4
J2 TCLK Cycle Period
t_JCYC
4
—
J3 TCLK Clock Pulse Width
t_JCW
26
—
J4 TCLK Rise and Fall Times
t_JCRF
0
3
J5 Boundary Scan Input Data Setup Time to TCLK Rise
t_BSDST
4
—
J6 Boundary Scan Input Data Hold Time after TCLK Rise
t_BSDHT
26
—
J7 TCLK Low to Boundary Scan Output Data Valid
t_BSDV
0
33
J8 TCLK Low to Boundary Scan Output High Z
t_BSDZ
0
33
J9 TMS, TDI Input Data Setup Time to TCLK Rise
t_TAPBST
4
—
J10 TMS, TDI Input Data Hold Time after TCLK Rise
t_TAPBHT
10
—
J11 TCLK Low to TDO Data Valid
t_TDODV
0
26
J12 TCLK Low to TDO High Z
t_TDODZ
0
8
J13 TRST Assert Time
t_TRSTAT
100
—
J14 TRST Setup Time (Negation) to TCLK High
t_TRSTST
10
—
1 _{JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.}
Unit
f_sys/3
t_CYC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCF532x ColdFire^® Microprocessor Data Sheet, Rev. 4
40
Freescale Semiconductor