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56F827 Datasheet, PDF (40/60 Pages) Motorola, Inc – 56F827 16-bit Hybrid Controller
SS
(Input)
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
SS is held High on master
tC
tR
tF
tCL
tCH
tF
tCL
tR
tDH
tDS
MSB in
tDI
tCH
Bits 14–1
tDV
LSB in
tDI(ref)
Master MSB out
tF
Bits 14–1
Master LSB out
tR
Figure 3-20 SPI Master Timing (CPHA = 0)
SS
(Input)
SCLK (CPOL = 0)
(Output)
SS is held High on master
tC
tF
tCL
tR
tCH
tF
tCL
SCLK (CPOL = 1)
(Output)
MISO
(Input)
tDV(ref)
tCH
MSB in
tDI
tR
Bits 14–1
tDV
tDS
tDH
LSB in
MOSI
(Output)
Master MSB out
Bits 14– 1
Master LSB out
tF
tR
Figure 3-21 SPI Master Timing (CPHA = 1)
56F827 Technical Data, Rev. 12
40
Freescale Semiconductor