MC68EN360AI25VL Datasheet, PDF (4/14 Pages) Freescale Semiconductor, Inc – MC68360 QUad Integrated Communication Controller

Freescale Semiconductor, Inc.
QUICC ARCHITECTURE OVERVIEW
The QUICC is 32-bit controller that is an extension of other members of the Freescale M68300 family. Like
other members of the M68300 family, the QUICC incorporates the intermodule bus (IMB). (The MC68302 is
an exception, having an M68000 bus on chip.) The IMB provides a common interface for all modules of the
M68300 family, which allows Freescale to develop new devices more quickly by using the library of existing
modules. Although the IMB definition always included an option for an on-chip 32-bit bus, the QUICC is the
first device to implement this option.
The QUICC is comprised of three modules: the CPU32+ core, the SIM60, and the CPM. Each module
utilizes the 32-bit IMB. The MC68360 QUICC block diagram is shown in Figure 1.
CPU32+
CORE
SIM 60
SYSTEM
PROTECTION
JTAG
PERIODIC
TIMER
CLOCK
GENERATION
OTHER
FEATURES
BREAKPOINT
LOGIC
DRAM
CONTROLLER
AND
CHIP SELECTS
TWO
IDMAs
IMB (32 BIT)
CPM
COMMUNICATIONS PROCESSOR
RISC
CONTROLLER
FOURTEEN SERIAL
DMAs
2.5-KBYTE
DUAL-PORT
RAM
INTERRUPT
CONTROLLER
SEVEN
SERIAL
CHANNELS
TIMER SLOT
ASSIGNER
OTHER
FEATURES
EXTERNAL
BUS
INTERFACE
FOUR
GENERAL-
PURPOSE
TIMERS
SYSTEM
I/F
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