MC44BC375U Datasheet, PDF (4/16 Pages) Freescale Semiconductor, Inc – PLL Tuned VHF (Channel 3 / 4)Audio / Video Modulator

TRANSIENT OUTPUT INHIBIT
To minimize the risk of interference to other channels while
the UHF PLL is acquiring a lock on the desired frequency, the
Sound and Video modulators are turned OFF at power-ON
(i.e., V_CC is switched from 0 V to 5.0 V or device is switched
from “Standby mode” to “Normal operation”).
There is a time-out of 263 ms until the output is enabled.
This allows the UHF PLL to settle to its programmed frequen-
cy. During the 263 ms time-out, the sound PLL current source
is set to 10 µA typical to speed up the locking time. After the
263 ms time-out, the current source is switched to 1.0 µA.
Use care when selecting loop filter components to ensure the
loop transient does not exceed this delay.
VIDEO SECTION
The modulator requires a composite video input with neg-
ative going sync pulses and a nominal level of 1.0 V_(pp). This
signal is AC coupled to the video input where the sync tip lev-
el is clamped.
The video modulation depth typical value is given for
1.0 V_CBVS input level. It can be adjusted to any lower value
by simply adding a resistive divider at video input, resulting in
a lower signal seen by the video input stage.
The video signal is then passed to a peak white clip circuit
whose function is to soft clip the top of the video waveform if
the amplitude from the sync tip to peak white goes too high.
In this way, over-modulation of the carrier by the video is
avoided. The clipping function is always engaged.
SOUND SECTION
The multivibrator oscillator is fully integrated and does not
require any external components. An internal low pass filter
and matched structure give a very low harmonics level.
The sound modulator system consists of an FM modulator
incorporating the sound subcarrier oscillator. The audio input
signal is AC coupled into the amplifier which then drives the
modulator.
The audio pre-emphasis circuit is a high-pass filter with an
external capacitor C1 and an internal resistor (100 kΩ typi-
cal). The recommended capacitor value (750 pF) is for M/N
standards, time constant is 75 µs and it is 470 pF for B/G
standards (50 µs).
The audio bandwidth specification is for 50 Hz to 15 KHz
range, with pre-emphasis circuit engaged. Without this pre-
emphasis circuit, it is possible to extend the audio bandwidth
to high frequencies, as there is no internal frequency limita-
tion (stereo application).
PLL SECTION — DIVIDERS
The reference divider is a fixed ÷128 resulting in a refer-
ence frequency of 31.25 KHz with a 4.0 MHz crystal. The
31.25 KHz reference frequency is used for both the UHF and
Sound PLLs.
The prescaler is a fixed ÷8 and is permanently engaged.
The VHF divider is also a fixed ÷8.
The programmable divider’s division ratio is controlled by
the CHS pin voltage in order to select channel 3 or channel 4.
PIN SELECTION
Pins CHS, PSS, and SFS are internally pulled up to 5.0 V.
By default (open condition), all pins are “HI”.
Table 2. Configuration Pin Settings
Pin No Pin Name LO (grounded) HI (open or +5.0 V)
1
CHS
CH4
CH3
2
PSS
14 dB
16 dB
9
PSave/ Power save Mode Normal Operation
LOP
LOP pin LO
LOP pin HI
(Low voltage)
(High impedance)
16
SFS
5.5 MHz
4.5 MHz
MC44BC375U
4
Application Specific Products
Freescale Semiconductor