68HC705P6A_1 Datasheet, PDF (39/134 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification — MC68HC705P6A
Section 4. Resets
4.1 Contents
4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.3 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.4 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.4.1 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.4.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . .40
4.2 Introduction
The MCU can be reset from three sources: one external input and two
internal reset conditions. The RESET pin is a Schmitt trigger input as
shown in Figure 4-1. The CPU and all peripheral modules will be reset
by the RST signal which is the logical OR of internal reset functions and
is clocked by PH1.
RESET
V_DD
OSC
DATA
ADDRESS
POWER-ON
RESET
(POR)
COP
WATCHDOG
(COPR)
D
RES
DFF
RST
TO CPU AND
PERIPHERALS
PH1
Figure 4-1. Reset Block Diagram
MC68HC705P6A — Rev. 1.0
General Release Specification
Resets
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