MSC8126 Datasheet, PDF (38/48 Pages) Freescale Semiconductor, Inc – Quad Digital Signal Processor

Table 30. JTAG Timing (continued)
No.
Characteristics
704
705
706
707
708
709
710
711
712
713
Note:
Boundary scan input data set-up time
Boundary scan input data hold time
TCK low to output data valid
TCK low to output high impedance
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO high impedance
TRST assert time
TRST set-up time to TCK low
All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.
All
frequencies
Min
5.0
20.0
0.0
0.0
5.0
20.0
0.0
0.0
100.0
30.0
Max
—
—
30.0
30.0
—
—
20.0
20.0
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK
(Input)
V_IH
703
V_M
V_IL
701
702
V_M
703
Figure 29. Test Clock Input Timing Diagram
TCK
(Input)
Data
Inputs
Data
Outputs
Data
Outputs
V_IL
706
707
V_IH
704
705
Input Data Valid
Output Data Valid
Figure 30. Boundary Scan (JTAG) Timing Diagram
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
38
Freescale Semiconductor