DSPB56366AG120 Datasheet, PDF (38/110 Pages) Freescale Semiconductor, Inc – 24-Bit Audio Digital Signal Processor

Table 3-8 SRAM Read and Write Accesses¹ (continued)
No.
Characteristics
Symbol
Expression²
Min
Max
Unit
101 Address and AA valid to WR assertion
t_AS
0.25 × T_C − 2.0
0.1
—
ns
[WS = 1]
1.25 × T_C − 2.0
[WS ≥ 4]
8.4
—
ns
102 WR assertion pulse width
t_WP
1.5 × T_C − 4.0 [WS = 1]
8.5
—
ns
All frequencies:
WS × T_C − 4.0
[2 ≤ WS ≤ 3]
12.7
—
ns
(WS − 0.5) × T_C − 4.0
25.2
—
ns
[WS ≥ 4]
103 WR deassertion to address not valid
t_WR
0.25 × T_C − 2.0
0.1
—
ns
[1 ≤ WS ≤ 3]
1.25 × T_C − 2.0
[4 ≤ WS ≤ 7]
8.4
—
ns
2.25 × T_C − 2.0
[WS ≥ 8]
16.7
—
ns
All frequencies:
1.25 × T_C − 4.0
[4 ≤ WS ≤ 7]
6.4
—
ns
2.25 × T_C − 4.0
[WS ≥ 8]
14.7
—
ns
104 Address and AA valid to input data valid
t_AA, t_AC (WS + 0.75) × T_C − 7.0
—
7.6
ns
[WS ≥ 1]
105 RD assertion to input data valid
t_OE
(WS + 0.25) × T_C − 7.0
—
3.4
ns
[WS ≥ 1]
106 RD deassertion to data not valid (data hold time) t_OHZ
0.0
—
ns
107 Address valid to WR deassertion³
t_AW
(WS + 0.75) × T_C − 4.0 10.6
—
ns
[WS ≥ 1]
108 Data valid to WR deassertion (data setup time) t_DS (t_DW) (WS − 0.25) × T_C − 3.0
3.2
—
ns
[WS ≥ 1]
3-12
DSP56366 Technical Data, Rev. 3.1
Freescale Semiconductor