MKL14Z32VFM4 Datasheet, PDF (36/47 Pages) Freescale Semiconductor, Inc – Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: PKL14 and MKL14

Peripheral operating requirements and behaviors
Table 23. SPI master mode timing on slew rate enabled pads
Num.
1
2
3
4
5
6
7
8
9
10
11
Symbol
f_op
t_SPSCK
Description
Frequency of operation
SPSCK period
t_Lead
t_Lag
t_WSPSCK
Enable lead time
Enable lag time
Clock (SPSCK) high or low time
t_SU
Data setup time (inputs)
t_HI
Data hold time (inputs)
t_v
Data valid (after SPSCK edge)
t_HO
Data hold time (outputs)
t_RI
Rise time input
t_FI
Fall time input
t_RO
Rise time output
t_FO
Fall time output
Min.
f_periph/2048
2 x t_periph
1/2
1/2
t_periph - 30
96
0
—
0
—
Max.
f_periph/2
2048 x
t_periph
—
—
1024 x
t_periph
—
—
52
—
t_periph - 25
Unit
Hz
ns
t_SPSCK
t_SPSCK
ns
ns
ns
ns
ns
ns
—
36
ns
1. For SPI0 f_periph is the bus clock (f_BUS). For SPI1 f_periph is the system clock (f_SYS).
2. t_periph = 1/f_periph
SS¹
(OUTPUT)
3
2
10
SPSCK
(CPOL = 0)
5
(OUTPUT)
5
SPSCK
10
(CPOL = 1)
(OUTPUT)
11
4
11
6
7
MISO
(INPUT)
MSB IN²
BIT 6 . . . 1
LSB IN
MOSI
(OUTPUT)
MSB OUT²
8
BIT 6 . . . 1
9
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 9. SPI master mode timing (CPHA = 0)
Note
1
2
—
—
—
—
—
—
—
—
—
KL14 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
36
Freescale Semiconductor, Inc.