56F807 Datasheet, PDF (36/60 Pages) Motorola, Inc – 56F807 16-bit Hybrid Processor

RESET
A0–A15,
D0–D15
PS, DS,
RD, WR
t_RAZ
t_RA
Figure 3-12 Asynchronous Reset Timing
t_RDA
First Fetch
First Fetch
IRQA,
IRQB
t_IRW
Figure 3-13 External Interrupt Timing (Negative-Edge-Sensitive)
A0–A15,
PS, DS,
RD, WR
IRQA,
IRQB
General
Purpose
I/O Pin
IRQA,
IRQB
First Interrupt Instruction Execution
t_IDM
a) First Interrupt Instruction Execution
t_IG
b) General Purpose I/O
Figure 3-14 External Level-Sensitive Interrupt Timing
56F807 Technical Data Technical Data, Rev. 15
36
Freescale Semiconductor