SCF5250LAG100 Datasheet, PDF (35/56 Pages) Freescale Semiconductor, Inc – Integrated ColdFire Microprocessor Data Sheet

Table 30. JTAG AC Timing Specifications (continued)
Num
Characteristic
Min
Max
J11 TCK falling to Boundary Scan Data Valid (signal from driven or three-state)
–
tbd
J12 TCK falling to Boundary Scan. Data High Impedance
–
tbd
Units
ns
ns
Figure 12 provides the SCLK input, SDATA output timing diagram for the IIS module and Table 31
provides the timing parameters.
SCLK (INPUT)
SDATAO1, 2 (OUTPUT)
TU
TD
Figure 12. SCLK Input, SDATA Output Timing Diagram
Table 31. SCLK Input, SDATA Output Timing Specifications
Num
Characteristic
TU SCLK fall to SDATAO rise
TD SCLK fall to SDATAO fall
Min
Max Units
–
25
ns
–
25
ns
Figure 13 provides the SCLK output, SDATA output timing diagram for the IIS module and Table 32
provides the timing parameters.
SCLK (OUTPUT)
SDATAO1, 2 (OUTPUT)
TU
TD
Figure 13. SCLK Output, SDATA Output Timing Diagram
Table 32. SCLK Output, SDATA Output Timing Specifications
Num
TU
TD
Characteristic
SCLK fall to SDATAO rise
SCLK fall to SDATAO fall
Min
Max Units
–
3
ns
–
3
ns
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
35