56F807_1 Datasheet, PDF (35/60 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Reset, Stop, Wait, Mode Select, and Interrupt Timing
3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing^1,5
Operating Conditions: V_SS = V_SSA = 0 V, V_DD = V_DDA = 3.0–3.6 V, T_A = –40° to +85°C, C_L ≤ 50pF
Characteristic
Symbol
Min
Max
Unit See Figure
RESET Assertion to Address, Data and Control Signals
t_RAZ
—
High Impedance
21
ns
3-12
Minimum RESET Assertion Duration²
OMR Bit 6 = 0
OMR Bit 6 = 1
t_RA
275,000T
—
ns
128T
—
ns
3-12
RESET Deassertion to First External Address Output
t_RDA
33T
34T
ns
3-12
Edge-sensitive Interrupt Request Width
t_IRW
1.5T
—
ns
3-13
IRQA, IRQB Assertion to External Data Memory Access
t_IDM
15T
Out Valid, caused by first instruction execution in the
interrupt service routine
—
ns
3-14
IRQA, IRQB Assertion to General Purpose Output Valid,
t_IG
16T
caused by first instruction execution in the interrupt
service routine
—
ns
3-14
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State³
t_IRI
13T
—
ns
3-15
IRQA Width Assertion to Recover from Stop State⁴
t_IW
2T
—
ns
3-16
Delay from IRQA Assertion to Fetch of first instruction
t_IF
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
—
275,000T ns
—
12T
ns
3-16
Duration for Level Sensitive IRQA Assertion to Cause
t_IRQ
the Fetch of First IRQA Interrupt Instruction (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
—
275,000T ns
—
12T
ns
3-17
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t_II
3-17
—
275,000T ns
—
12T
ns
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
not the minimum required so that the IRQA interrupt is accepted.
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
5. Parameters listed are guaranteed by design.
56F807 Technical Data Technical Data, Rev. 16
Freescale Semiconductor
35