DSP56374 Datasheet, PDF (33/64 Pages) Motorola, Inc – high density CMOS device with 3.3 V inputs and outputs

Reset, Stop, Mode Select, and Interrupt Timing
Table 20. Reset, Stop, Mode Select, and Interrupt Timing (continued)
No.
Characteristics
Expression
Min Max Unit
21 Interrupt Requests Rate¹
• ESAI, ESAI_1, SHI, Timer
12 x T_C
— 80.0 ns
• DMA
• IRQ, NMI (edge trigger)
• IRQ (level trigger)
22 DMA Requests Rate
• Data read from ESAI, ESAI_1, SHI
8 x T_C
8 x T_C
12 x T_C
6 x T_C
— 53.0 ns
— 53.0 ns
— 80.0 ns
— 40.0 ns
• Data write to ESAI, ESAI_1, SHI
7 x T_C
— 46.7 ns
• Timer
2 x T_C
— 13.4 ns
• IRQ, NMI (edge trigger)
3 x T_C
— 20.0 ns
Note:
1 _{When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through}
21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is
recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
2 _{For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will}
be defined by the OMR Bit 6 settings.
For PLL enable, (if bet 12 of the PCTL register is 0), the PLL is shutdown during Stop. Recovering from Stop
requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range
of 0.5 ms.
3 _{Periodically sampled and not 100% tested.}
4 _{RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is}
active and valid. When the V_DD is valid, but the other “required RESET duration” conditions (as specified
above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant
power consumption and heat-up. Designs should minimize this state to the shortest possible duration.
V_IH
RESET
11
13
10
All Pins
Reset Value
Figure 3. Reset Timing
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
33