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56F803 Datasheet, PDF (33/52 Pages) Motorola, Inc – 56F803 16-bit Hybrid Controller
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing (Continued)1, 5
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Symbol
Min
Max
Unit See Figure
Edge-sensitive Interrupt Request Width
tIRW
IRQA, IRQB Assertion to External Data Memory
tIDM
Access Out Valid, caused by first instruction execution
in the interrupt service routine
IRQA, IRQB Assertion to General Purpose Output
tIG
Valid, caused by first instruction execution in the
interrupt service routine
1.5T
15T
16T
—
ns
Figure 3-13
—
ns
Figure 3-14
—
ns
Figure 3-14
IRQA Low to First Valid Interrupt Vector Address Out
tIRI
13T
recovery from Wait State3
—
ns
Figure 3-15
IRQA Width Assertion to Recover from Stop State4
tIW
2T
—
ns
Figure 3-16
Delay from IRQA Assertion to Fetch of first instruction
tIF
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
Figure 3-16
—
275,000T ns
—
12T
ns
Duration for Level Sensitive IRQA Assertion to Cause
tIRQ
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
Figure 3-17
—
275,000T ns
—
12T
ns
Delay from Level Sensitive IRQA Assertion to First
tII
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
Figure 3-17
—
275,000T ns
—
12T
ns
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
not the minimum required so that the IRQA interrupt is accepted.
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
5. Parameters listed are guaranteed by design.
56F803 Technical Data, Rev. 15
Freescale Semiconductor
33