MSC8126_08 Datasheet, PDF (32/48 Pages) Freescale Semiconductor, Inc – Quad Digital Signal Processor

Electrical Characteristics
2.5.7 TDM Timing
Table 21. TDM Timing
No.
300
301
302
303
304
305
306
307
308
309
310
Notes:
Characteristic
Expression
Ref = CLKIN
Min Max
Units
TDMxRCLK/TDMxTCLK
TC¹
16
—
ns
TDMxRCLK/TDMxTCLK high pulse width
(0.5 ± 0.1) × TC
7
—
ns
TDMxRCLK/TDMxTCLK low pulse width
(0.5 ± 0.1) × TC
7
—
ns
TDM receive all input set-up time
1.3
—
ns
TDM receive all input hold time
TDMxTCLK high to TDMxTDAT/TDMxRCLK output active^2,3
TDMxTCLK high to TDMxTDAT/TDMxRCLK output valid^2,3
All output hold time⁵
TDMxTCLK high to TDmXTDAT/TDMxRCLK output high impedance^2,3
TDMxTCLK high to TDMXTSYN output valid²
TDMxTSYN output hold time⁵
1.0
—
ns
2.8
—
ns
—
8.8
ns
2.5
—
ns
—
10.5
ns
—
8.5
ns
2.5
—
ns
1. Values are based on a a maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz.
2. Values are based on 20 pF capacitive load.
3. When configured as an output, TDMxRCLK acts as a second data link. See the MSC8126 Reference Manual for details.
4. CLKOUT synchronization is not supported for cores operating at above 400 MHz.
5. Values are based on 10 pF capacitive load.
TDMxRCLK
303
TDMxRDAT
300
301
302
304
TDMxRSYN
304
303
Figure 18. TDM Inputs Signals
TDMxTCLK
TDMxTDAT
TDMxRCLK
TDMxTSYN
300
301
302
306
305
309
Figure 19. TDM Output Signals
308
307
310
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 14
32
Freescale Semiconductor