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MC9S08AW60MFGE Datasheet, PDF (31/324 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU) | |||
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Chapter 2 Pins and Connections
Table 2-1. Pin Sharing Priority
Lowest <- Pin Function Priority -> Highest
Port Pins
Alternate Function Alternate Function
Reference1
PTF3âPTF0
TPM1CH5â
TPM1CH2
Chapter 10, âTimer/PWM (S08TPMV2)â
PTG4âPTG0 KBI1P4âKBI1P0
Chapter 9, âKeyboard Interrupt (S08KBIV1)â
PTG6âPTG5 EXTALâXTAL
Chapter 8, âInternal Clock Generator (S08ICGV4)â
1 See the listed chapter for information about modules that share these pins.
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pinâs output buffer. See the Chapter 6, âParallel Input/Outputâ chapter for more details.
Pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever the pin
is acting as an input even if it is being controlled by an on-chip peripheral module. When the PTD7, PTD3,
PTD2, and PTG4 pins are controlled by the KBI module and are conï¬gured for rising-edge/high-level
sensitivity, the pullup enable control bits enable pulldown devices rather than pullup devices.
NOTE
When an alternative function is ï¬rst enabled it is possible to get a spurious
edge to the module, user software should clear out any associated ï¬ags
before interrupts are enabled. Table 2-1 illustrates the priority if multiple
modules are enabled. The highest priority module will have control over the
pin. Selecting a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority module. It is
recommended that all modules that share a pin be disabled before enabling
another module.
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
31
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