10XS3435 Datasheet, PDF (30/51 Pages) Freescale Semiconductor, Inc – Quad High Side Switch (Dual 10 mOhm, Dual 35 mOhm)

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The calibratable clock is used, instead of the clock from
IN0 input, when CLOCK_sel is set to [1].
FAIL-SAFE MODE
The 10XS3435 is in Fail-safe mode when:
• V_PWR is within the normal voltage range,
• wake-up = 1,
• fail = 1,
• fault = 0.
Watchdog
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or IN_ON[0:3] or
RST input pin transitions from logic [0] to logic [1]. The WAKE
input is capable of being pulled up to VPWR with a series of
limiting resistance limiting the internal clamp current
according to the specification.
The watchdog timeout is a multiple of an internal oscillator.
As long as the WD bit (D15) of an incoming SPI message is
toggled within the minimum watchdog timeout period
(WDTO), the device will operate normally.
Fail-Safe conditions
If an internal watchdog time-out occurs before the WD bit
for FSI open (Table 9) or in case of V_DD failure condition
(V_DD< V_DD(FAIL))) for VDD_FAIL_en bit is set to logic [1], the
device will revert to a Fail-safe mode until the WD bit is written
to logic [1] (see Fail-safe to Normal mode transition
paragraph) and V_DD is within the normal voltage range.
Table 9. SPI Watchdog Activation
Typical RFSI (Ω)
Watchdog
0 (shorted to ground)
Disabled
(open)
Enable
During the Fail-safe mode, the outputs will depend on the
corresponding input. The SPI register content is reset to their
default value (except POR bit) and fault protections are fully
operational.
The Fail-safe mode can be detected by monitoring the NM
bit is set to [0].
NORMAL & FAIL-SAFE MODE TRANSITIONS
Transition Fail-safe to Normal mode
To leave the Fail-safe mode, V_DD must be in nominal
voltage and the microcontroller has to send a SPI command
with WDIN bit set to logic [1] ; the other bits are not
considered. The previous latched faults are reset by the
transition into Normal mode (autoretry included).
Moreover, the device can be brought out of the Fail-safe
mode due to watchdog timeout issue by forcing the FSI pin to
logic [0].
Transition Normal to Fail-Safe mode
To leave the Normal mode, a Fail-safe condition must
occurred (fail=1). The previous latched faults are reset by the
transition into Fail-safe mode (autoretry included).
FAULT MODE
The 10XS3435 is in Fault mode when:
• V_PWR and V_DD are within the normal voltage range,
• wake-up = 1,
• fail = X,
• fault=1.
This device indicates the faults below as they occur by
driving the FS pin to logic [0] for RST input is pulled up:
•Over-temperature fault,
•Over-current fault,
•Severe short-circuit fault,
•Output(s) shorted to VPWR fault in OFF state,
•Open-load fault in OFF state,
•Over-voltage fault (enabled by default),
•Under-voltage fault.
The FS pin will automatically return to logic [1] when the
fault condition is removed, except for over-current, severe
short-circuit, over-temperature and under-voltage which will
be reset by a new turn-on command (each fault_control
signal to be toggled).
Fault information is retained in the SPI fault register and is
available (and reset) via the SO pin during the first valid SPI
communication.
The Open load fault in ON state is only reported through
SPI register without effect on the corresponding output state
(HS[x]) and the FS pin.
10XS3435
30
Analog Integrated Circuit Device Data
Freescale Semiconductor