MC9S12DG256MPVE Datasheet, PDF (3/14 Pages) Freescale Semiconductor, Inc – 16-Bit Microcontroller

Freescale Semiconductor, Inc.
Table 1 List of MC9S12D-Family members
Flash RAM EEPROM Package Device CAN J1850 SCI SPI IIC
DP512
5
1
2
3
1
512K 14K
4K 112LQFP DT512
3
0
2
3
1
DJ512
2
1
2
3
1
DT256
3
0
2
3
1
112LQFP DJ256
2
1
2
3
1
256K 12K
4K
DG256
2
0
2
3
1
DJ256
2
1
2
3
1
80QFP
DG256
2
0
2
3
1
DT128
3
0
2
2
1
112LQFP DJ128
2
1
2
2
1
128K 8K
2K
DG128
2
0
2
2
1
DJ128
2
1
2
2
1
80QFP
DG128
2
0
2
2
1
64K 4K
DJ64
112LQFP
D64
1K
DJ64
80QFP
D64
1
1
2
1
1
1
0
2
1
1
1
1
2
1
1
1
0
2
1
1
32K 2K
1K
80QFP D32
1
0
2
1
0
A/D PWM I/O
2/16 8
91
2/16 8
91
2/16 8
91
2/16 8
91
2/16 8
91
2/16 8
91
1/8
7
59
1/8
7
59
2/16 8
91
2/16 8
91
2/16 8
91
1/8
7
59
1/8
7
59
2/16 8
91
2/16 8
91
1/8
7
59
1/8
7
59
1/8
7
59
• Pin out explanations:
— A/D is the number of modules/total number of A/D channels.
— I/O is the sum of ports capable to act as digital input or output.
112 Pin Packages:
Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 7, M = 8, P = 8, S = 8, T = 8, PAD = 16 input
only.
22 inputs provide Interrupt capability (H =8, P= 8, J = 4, IRQ, XIRQ)
80 Pin Packages:
Port A = 8, B = 8, E = 6 + 2 input only, J = 2, M = 6, P = 7, S = 4, T = 8, PAD = 8 input only.
11 inputs provide Interrupt capability (P= 7, J = 2, IRQ, XIRQ)
— CAN0 pins are shared between J1850 pins.
— CAN0 can be routed under software control from PM1:0 to pins PM3:2 or PM5:4 or PJ7:6.
— CAN4 pins are shared between IIC pins.
— CAN4 can be routed under software control from PJ7:6 to pins PM5:4 or PM7:6.
— Versions with 4 CAN modules will have CAN0, CAN1, CAN2 and CAN4.
— Versions with 3 CANs modules will have CAN0, CAN1 and CAN4.
— Versions with 2 CAN modules will have CAN0 and CAN4.
— Versions with one CAN module will have CAN0.
— Versions with 2 SPI modules will have SPI0 and SPI1.
— Versions with 1 SPI will have SPI0.
— SPI0 can be routed to either Ports PS7:4 or PM5:2.
— SPI2 pins are shared with PWM7:4; In 112 pin versions SPI2 can be routed under software control to
PH7:4. In 80 pin packages SS-signal of SPI2 is not bonded out!
NOTE
CAN and SPI routing features are not available on the 1st PC9S12DP256 mask set 0K36N!
PRODUCT PROPOSAL, Rev 6^F.^o1^r, 2^M3-^oO^rc^et-^I0ⁿ2^{formation On This Product,}
3
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