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MC68QH302 Datasheet, PDF (3/6 Pages) Freescale Semiconductor, Inc – Quad HDLC Integrated Multiprotocol Processor | |||
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Freescale Semiconductor, Inc.
1.1 FEATURES
The main features of the MC68QH302 are as follows (new features indicated in bold):
⢠MC68000/MC68008 microprocessor core (may be disabled to use the IMP as a peripheral)
⢠Serial interface block including:
â Independent direct memory access (IDMA) controller
â Interrupt controller with two modes of operation
â Parallel I/O ports, some with interrupt capability
â On-chip 1152 bytes of dual-ported RAM
â Three timers, including a software watchdog timer
â Four programmable chip-select lines with wait-state logic
â Programmable address mapping of dual-ported RAM and IMP registers
â On-chip clock generator with an output clock signal
â System control
â System control register
â Bus arbitration logic with low-interrupt latency support
â Hardware watchdog for monitoring bus activity
â Low power (standby) modes
â Disable CPU logic (M68000)
â Freeze control for debugging selected on-chip peripherals
â DRAM refresh controller
⢠CP including:
â Main controller (RISC processor)
â Three physical full-duplex serial communication controllers (SCCs) with the following
protocols:
â HDLC/SDLC
â UART
â Totally transparent
â V.110
â SCC1 can support two logical HDLC or transparent channels running QH protocol
â Eight serial DMA channels dedicated to the four serial channels
â Capability to send /receive up to eight buffers/frames without M68000 core intervention
â Flexible physical interface accessible by SCCs for interchip digital link (IDL), general circuit
interface (GCI, also called IOM2), pulse code modulation (PCM), and nonmultiplexed serial
interface (NMSI) operation
â Serial communication port (SCP) for synchronous communication
â Serial management controllers (SMCs) for IDL and GCI channels
⢠Application development system available with M68302FADS.
MC68QH302 Technical Summary
For More Information On This Product,
Go to: www.freescale.com
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