MC33903_4_5 Datasheet, PDF (29/106 Pages) Freescale Semiconductor, Inc – SBC Gen2 with CAN High Speed and LIN Interface

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 7. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5 V  V_SUP  28 V, - 40 C  T_A  125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T_{A =} 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC ACCORDING TO LIN PHYSICAL
LAYER SPECIFICATION
BUS LOAD R_BUS AND C_BUS 1.0 NF / 1.0 K, 6.8 NF / 660 , 10 NF / 500 . SEE Figure 18, PAGE 32.
Duty Cycle 1:
TH_REC(MAX) = 0.744 * V_SUP
TH_DOM(MAX) = 0.581 * V_SUP
D1 = t_{BUS_REC(MIN)}/(2 x t_BIT), t_BIT = 50 µs, 7.0 V V_SUP18 V
D1
0.396
-
-
Duty Cycle 2:
TH_REC(MIN) = 0.422 * V_SUP
TH_DOM(MIN) = 0.284 * V_SUP
D2 = t_{BUS_REC(MAX)}/(2 x t_BIT), t_BIT = 50 µs, 7.6 V V_SUP18 V
D2
-
-
0.581
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER
SPECIFICATION
BUS LOAD R_BUS AND C_BUS 1.0 NF / 1.0 K, 6.8 NF / 660 , 10 NF / 500 . MEASUREMENT THRESHOLDS. SEE Figure 19, PAGE 33.
Duty Cycle 3:
TH_REC(MAX) = 0.778 * V_SUP
TH_DOM(MAX) = 0.616 * V_SUP
D3 = t_{BUS_REC(MIN)}/(2 x t_BIT), t_BIT = 96 µs, 7.0 V V_SUP18 V
D3
0.417
-
-
Duty Cycle 4:
TH_REC(MIN) = 0.389 * V_SUP
TH_DOM(MIN) = 0.251 * V_SUP
D4 = t_{BUS_REC(MAX)}/(2 x t_BIT), t_BIT = 96 µs, 7.6 V V_SUP18 V
D4
-
-
0.590
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE
LIN Fast Slew Rate (Programming Mode)
SR_FAST
-
20
-
V / s
LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS
V_SUP FROM 7.0 TO 18 V, BUS LOAD R_BUS AND C_BUS 1.0 NF / 1.0 K, 6.8 NF / 660 , 10 NF / 500 . SEE Figure 18, PAGE 32.
Propagation Delay and Symmetry (See Figure 18, page 31 and Figure 19,
s
page 33)
Propagation Delay of Receiver, t_{REC_PD} = MAX (t_{REC_PDR}, t_{REC_PDF})
t _{REC_PD}
-
4.2
6.0
Symmetry of Receiver Propagation Delay, t_{REC_PDF} - t_{REC_PDR}
t _{REC_SYM}
- 2.0
-
2.0
Bus Wake-up Deglitcher (LP V_DD OFF and LP V_DD ON modes) (See Figure 20, _tPROPWL
42
70
95
s
page 32 for LP V_DD OFF mode and Figure 21, page 33 for LP mode)
Bus Wake-up Event Reported
From LP V_DD OFF mode
From LP V_DD ON mode
t _{WAKE_LPVDD}
-
OFF
t _{WAKE_LPVDD}
1.0
ON
s
-
1500
-
12
TXD Permanent Dominant State Delay (Guaranteed by design)
t _TXDDOM
0.65
1.0
1.35
s
Analog Integrated Circuit Device Data
Freescale Semiconductor
33903/4/5
29