56F8347 Datasheet, PDF (29/176 Pages) Freescale Semiconductor, Inc – 16-BIT HYBRID CONTROLLERS

Signal Pins
Table 2-2 Signal and Package Information for the 160-Pin LQFP
Signal Name Pin No. Type
State
During
Reset
Signal Description
TDO
TRST
140
Output Tri-stated Test Data Output — This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
136
Schmitt
Input,
Test Reset — As an input, a low signal on this pin provides a reset
Input pulled high signal to the JTAG TAP controller. To ensure complete hardware
internally reset, TRST should be asserted whenever RESET is asserted.
The only exception occurs in a debugging environment when a
hardware device reset is required and the JTAG/EOnCE module
must not be reset. In this case, assert RESET, but do not assert
TRST.
PHASEA0
155
Schmitt
Input
Input
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
Phase A — Quadrature Decoder 0, PHASEA input
(TA0)
Schmitt
Input/
Output
Input
TA0 — Timer A, Channel 0
(GPIOC4)
Schmitt
Input/
Output
Input
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is PHASEA0.
PHASEB0
156
Schmitt
Input
Input
To deactivate the internal pull-up resistor, clear bit 4 of the
GPIOC_PUR register.
Phase B — Quadrature Decoder 0, PHASEB input
(TA1)
Schmitt
Input/
Output
Input
TA1 — Timer A, Channel
(GPIOC5)
Schmitt
Input/
Output
Input
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is PHASEB0.
To deactivate the internal pull-up resistor, clear bit 5 of the
GPIOC_PUR register.
56F8347 Technical Data, Rev. 3.0
Freescale Semiconductor
29
Preliminary