56F802 Datasheet, PDF (29/40 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

JTAG Timing
ADC analog input
1
2
3
4
1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
4. Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only connected to it at
sampling time. (1pf)
Figure 3-13 Equivalent Analog Input Circuit
3.10 JTAG Timing
Table 3-14 JTAG Timing ^{1, 3}
Operating Conditions: V_SS = V_SSA = 0 V, V_DD = V_DDA = 3.0–3.6 V, T_A = –40° to +85°C, C_L ≤ 50 pF
Characteristic
Symbol
Min
Max
Unit
TCK frequency of operation²
f_OP
DC
10
TCK cycle time
t_CY
100
—
TCK clock pulse width
t_PW
50
—
TMS, TDI data setup time
t_DS
0.4
—
TMS, TDI data hold time
t_DH
1.2
—
TCK low to TDO data valid
t_DV
—
26.6
TCK low to TDO tri-state
t_TS
—
23.5
TRST assertion time
t_TRST
50
—
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5ns.
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
MHz
ns
ns
ns
ns
ns
ns
ns
56F802 Technical Data, Rev. 7
Freescale Semiconductor
29