MSC7119 Datasheet, PDF (28/56 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Electrical Characteristics
Figure 7 provides the AC test load for the DDR DRAM bus.
Output
Z₀ = 50 Ω
R_L = 50 Ω
V_OUT
Figure 7. DDR DRAM AC Test Load
Table 19. DDR DRAM Measurement Conditions
Symbol
V_TH1
V_OUT²
Notes: 1. Data input threshold measurement point.
2. Data output measurement point.
DDR DRAM
V_REF ± 0.31 V
0.5 × V_DDM
Unit
V
V
2.5.5 TDM Timing
Table 20. TDM Timing
No.
300
301
302
303
304
305
306
307
308
309
310
311
Notes:
Characteristic
Expression
Min
Max
Units
TDMxRCK/TDMxTCK
TC
20.0
—
ns
TDMxRCK/TDMxTCK High Pulse Width
0.4 × TC
8.0
—
ns
TDMxRCK/TDMxTCK Low Pulse Width
0.4 × TC
8.0
—
ns
TDM all input Setup time
3.0
—
ns
TDMxRD Hold time
3.5
—
ns
TDMxTFS/TDMxRFS input Hold time
2.0
—
ns
TDMxTCK High to TDMxTD output active
4.0
—
ns
TDMxTCK High to TDMxTD output valid
—
14.0
ns
TDMxTD hold time
2.0
—
ns
TDMxTCK High to TDMxTD output high impedance
—
10.0
ns
TDMxTFS/TDMxRFS output valid
—
13.5
ns
TDMxTFS/TDMxRFS output hold time
2.5
—
ns
1. Output values are based on 30 pF capacitive load.
2. Inputs are referenced to the sampling that the TDM is programmed to use. Outputs are referenced to the programming edge
they are programmed to use. Use of the rising edge or falling edge as a reference is programmable. Refer to the MSC711x
Reference Manual for details. TDMxTCK and TDMxRCK are shown using the rising edge.
300
301
302
TDMxRCK
303
TDMxRD
303
TDMxRFS
304
305
310
311
TDMxRFS (output)
Figure 8. TDM Receive Signals
MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6
28
Freescale Semiconductor