MC33696 Datasheet, PDF (28/64 Pages) Freescale Semiconductor, Inc – PLL Tuned UHF Transceiver for Data Transfer Applications

Configuration, Command, and Status Registers
17.1 Configuration Registers
Figure 19 describes configuration register 1, CONFIG1.
Bit Name
Reset Value
Bit 7
LOF1
1
Bit 6
LOF0
0
Bit 5
Bit 4
Bit 3
Bit 2
CF1
CF0
RESET
SL
0
1
0
0
Figure 19. CONFIG1 Register
Bit 1
LVDE
0
Bit 0
CLKE
1
Addr
$00
Table 9. LOF[1:0] and CF[1:0] Setting Versus Carrier Frequency
Carrier Frequency
304 MHz
315 MHz
426 MHz
434 MHz
868 MHz
915 MHz
LOF1
LOF0
CF1
CF0
0
0
0
0
1
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
RESET is a global reset. The bit is cleared internally, after use.
0 = no action
1 = reset all registers and counters
SL (Switch Level) selects the active level of the SWITCH output pin.
Table 10. Active Level of SWITCH Output Pin
SL
Transceiver Function Level on SWITCH
0
Receiving
Transmitting
1
Transmitting
Receiving
Low
High
Low
High
LVDE (Low Voltage Detection Enable) enables the low voltage detection function.
0 = disabled
1 = enabled
NOTE
This bit is cleared by POR. In the event of a complete loss of the supply
voltage, LVD is disabled at power-up, but the information is not lost as the
status bit LVDS is set by POR.
CLKE (Clock Enable) controls the DATACLK output buffer.
0 = DATACLK remains low
1 = DATACLK outputs F_dataclk
MC33696 Data Sheet, Rev. 9
28
Freescale Semiconductor