MC12311CHN Datasheet, PDF (28/40 Pages) Freescale Semiconductor, Inc – This section provides a simplified block diagram and highlights MC12311 features

Table 16. Control Timing (continued)
Num C
Rating
Symbol
Min
Typ¹
Max Unit
Keyboard interrupt pulse width
8 D Asynchronous path²
Synchronous path⁴
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)⁵
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
9C
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t_ILIH, t_IHIL
100
—
1.5 x t_cyc
—
t_Rise, t_Fall
—
8
—
31
t_Rise, t_Fall
—
7
—
24
—
—
ns
—
ns
—
—
ns
—
10
Voltage regulator recovery time
t_VRR
—
4
—
μs
1 _{Typical values are based on characterization data at VDD = 3.0V, 25°C unless otherwise stated.}
2 _{This is the shortest pulse that is guaranteed to be recognized as a reset or interrupt pin request. Shorter pulses are not}
guaranteed to override reset requests from internal sources.
3 _{To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD}
rises above V_LVD.
4 _{This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or}
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
5 _{Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 85°C.}
RESET PIN
t_extrst
Figure 13. Reset Timing
t_IHIL
KBIPx
IRQ/KBIPx
t_ILIH
Figure 14. IRQ/KBIPx Timing
8.4.6 TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
MC12311 Advance Information, Rev. 1.0
28
Freescale Semiconductor