908E626 Datasheet, PDF (28/38 Pages) Freescale Semiconductor, Inc – Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
HVDD_OCF — HVDD Output Overcurrent Flag Bit
This read / write flag is set on an overcurrent condition at
the HVDD terminal. Clear HVDD_OCF and enable the output
by writing a logic [1] to the HVDD_OCF Flag. Reset clears the
HVDD_OCF bit. Writing a logic [0] to HVDD_OCF has no
effect.
• 1 = Overcurrent condition on HVDD has occurred.
• 0 = No overcurrent condition on HVDD has occurred.
LVF — Low-Voltage Bit
This read only bit is a copy of the LVF bit in the Interrupt
Flag Register.
• 1 = Low-voltage condition has occurred.
• 0 = No low-voltage condition has occurred.
HVF — High-Voltage Sensor Bit
This read-only bit is a copy of the HVF bit in the Interrupt
Flag Register.
• 1 = High-voltage condition has occurred.
• 0 = No high-voltage condition has occurred.
HB_OCF — H-Bridge Overcurrent Flag Bit
This read / write flag is set on an overcurrent condition at
the H-Bridges. Clear HB_OCF and enable the H-Bridge
driver by writing a logic [1] to HB_OCF. Reset clears the
HB_OCF bit. Writing a logic [0] to HB_OCF has no effect.
• 1 = Overcurrent condition on H-Bridges has occurred.
• 0 = No overcurrent condition on H-Bridges has
occurred.
HTF — Overtemperature Status Bit
This read-only bit is a copy of the HTF bit in the Interrupt
Flag Register.
• 1 = Overtemperature condition has occurred.
• 0 = No overtemperature condition has occurred.
AUTONOMOUS WATCHDOG (AWD)
The Autonomous Watchdog module allows to protect the
CPU against code runaways.
The AWD is enabled if AWDRE in the AWDCTL Register
is set. If this bit is cleared, the AWD oscillator is disabled and
the watchdog switched off.
Watchdog
The watchdog function is only available in RUN mode. On
setting the AWDRE bit, watchdog functionality in RUN mode
is activated. Once this function is enabled, it is not possible to
disable it via software.
If the timer reaches end value and AWDRE is set, a
system reset is initiated. Operations of the watchdog function
cease in STOP mode. Normal operation will be continued
when the system is back to RUN mode.
To prevent a watchdog reset, the watchdog timeout
counter must be reset before it reaches the end value. This is
done by a write to the AWDRST bit in the AWDCTL Register.
Autonomous Watchdog Control Register (AWDCTL)
Register Name and Address: AWDCTL - $0a
Bit7 6
5
4
3
2
1
Read 0 0
0
0
0
AWDRE ₍₁₄₎
(14)
0
Write
AWDRST
Reset 0 0
0
0
0
0
0
Notes
16. This bit must always be set to 0.
Bit 0
AWDR
0
AWDRST — Autonomous Watchdog Reset Bit
This write-only bit resets the Autonomous Watchdog
timeout period. AWDRST always reads 0. Reset clears
AWDRST bit.
• 1 = Reset AWD and restart timeout period.
• 0 = No effect.
AWDRE — Autonomous Watchdog Reset Enable Bit
This read / write bit enables resets on AWD time-outs. A
reset on the RST_A is asserted when the Autonomous
Watchdog has reached the timeout and the Autonomous
Watchdog is enabled. AWDRE is one-time setable (write
once) after each reset. Reset clears the AWDRE bit.
• 1 = Autonomous watchdog enabled.
• 0 = Autonomous watchdog disabled.
AWDR — Autonomous Watchdog Rate Bit
This read / write bit selects the clock rate of the
Autonomous Watchdog. Reset clears the AWDR bit.
• 1 = Fast rate selected (10 ms).
• 0 = Slow rate selected (20 ms).
VOLTAGE REGULATOR
The 908E626 chip contains a low-power, low-drop voltage
regulator to provide internal power and external power for the
MCU. The V_DD regulator accepts a unregulated input supply
and provides a regulated V_DD supply to all digital sections of
the device. The output of the regulator is also connected to
the VDD terminal to provide the 5.0 V to the microcontroller.
908E626
28
Analog Integrated Circuit Device Data
Freescale Semiconductor