MC9S08AC60CFGE Datasheet, PDF (270/350 Pages) Freescale Semiconductor, Inc – 40-MHz HCS08 CPU (central processor unit)

Timer/PWM Module (S08TPMV3)
Table 15-8. Mode, Edge, and Level Selection (continued)
CPWMS
X
MSnB:MSnA ELSnB:ELSnA
XX
00
1
XX
10
X1
Mode
Configuration
Pin is not controlled by TPM. It is reverted to general
purpose I/O or other peripheral control
Center-aligned
PWM
High-true pulses (clear output on
channel match when TPM counter
is counting up)
Low-true pulses (set output on
channel match when TPM counter
is counting up)
15.5.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel registers are cleared by
reset.
7
6
5
4
3
2
R
Bit 15
14
13
12
11
10
W
1
0
9
Bit 8
Reset
0
0
0
0
0
0
0
0
Figure 15-13. TPM Channel Value Register High (TPMxCnVH)
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 15-14. TPM Channel Value Register Low (TPMxCnVL)
In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes
into a buffer where they remain latched until the other half is read. This latching mechanism also resets
(becomes unlatched) when the TPMxCnSC register is written (whether BDM mode is active or not). Any
write to the channel registers will be ignored during the input capture mode.
When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxCnSC register)
such that the buffer latches remain in the state they were in when the BDM became active, even if one or
both halves of the channel register are read while BDM is active. This assures that if the user was in the
middle of reading a 16-bit register when BDM became active, it will read the appropriate value from the
other half of the 16-bit value after returning to normal execution. The value read from the TPMxCnVH
and TPMxCnVL registers in BDM mode is the value of these registers and not the value of their read
buffer.
In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value
into a buffer. After both bytes are written, they are transferred as a coherent 16-bit value into the
timer-channel registers according to the value of CLKSB:CLKSA bits and the selected mode, so:
MC9S08AC60 Series Data Sheet, Rev. 3
270
Freescale Semiconductor