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MC9S08MP16VLC Datasheet, PDF (27/36 Pages) Freescale Semiconductor, Inc – MC9S08MP16 Series Data Sheet
Electrical Characteristics
Table 15. Programmable Gain Amplifier Electrical Specifications (continued)
Num C
Parameter
4 D Differential input voltage
5
T Linearity (@ voltage gain)1
• 1x
• 2x
• 4x
• 8x
• 16x
• 32x
Symbol
Min
( ) VDIFFMAX
– V----2-D----D----A-G----–-a---i-1-n--.--4-
LV
1 – 1/2 LSB
2 – 1/2 LSB
4 – 1 LSB
8 – 1 LSB
16 – 4 LSB
32 – 4 LSB
Typical
0
1
2
4
8
16
32
Max
V-----D----D----A-----–-----1---.--4-
2  Gain
1 + 1/2 LSB
2 + 1/2 LSB
4 + 1 LSB
8 + 1 LSB
16 + 4 LSB
32 + 4 LSB
Unit
V
V/V
6 T Max gain error
7a D PGA clock
• normal mode (LP=0)
• low power mode (LP=1)
7b D PGA sampling frequency3
EG
fPGA
fSAMPL
8 D Input signal bandwidth
BW
9 D Charge pump clock frequency
fcpclk
1 LSB in 12-bit resolution
2 8 MHz is required for PGA achieving 1 s sampling time.
3 ADC in 12-bit mode, long sampling time, fADC = fPGA
—
1
2
%
MHz
—
82
82
—
4
4
—
-------------------------------------------------1---------------------------------------------------


-1---2-----+-----1---8----------Nf--P--U--G--M--A---_----C----L---K----_----G----S---
+
----4---3------
fADC
+
------5------
fBUS
—
Samples
per second
0
fSAMPL  8
fSAMPL  2
Hz
100
fPGA  4
—
Hz
2.14 AC Characteristics
This section describes timing characteristics for each peripheral system.
2.14.1 Control Timing
Table 16. Control Timing
Num
1
2
3
4
5
6
C
Rating
Symbol
D
Bus frequency
(tcyc = 1/fBus)
–40 to 105 C
–40 to 125 C
P Internal low power oscillator period
D External reset pulse width2
D Reset low drive
D BKGD/MS setup time after issuing background debug force
reset to enter user or BDM modes
D BKGD/MS hold time after issuing background debug force
reset to enter user or BDM modes 3
fBus
fBus
tLPO
textrst
trstdrv
tMSSU
tMSH
Min
DC
DC
700
100
34 x tcyc
500
100
Typ1
—
—
—
—
—
—
—
Max
25.67
20
1300
—
—
—
Unit
MHz
MHz
s
ns
ns
ns
—
s
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
27