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K51P64M72SF1 Datasheet, PDF (27/74 Pages) Freescale Semiconductor, Inc – K51 Sub-Family | |||
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Peripheral operating requirements and behaviors
Table 13. MCG specifications (continued)
Symbol Description
Min.
floc_high Loss of external clock minimum frequency â
RANGE = 01, 10, or 11
(16/5) x
fints_t
FLL
ffll_ref FLL reference frequency range
31.25
fdco
DCO output
Low range (DRS=00)
20
frequency range
640 Ã ffll_ref
Mid range (DRS=01)
40
1280 Ã ffll_ref
Mid-high range (DRS=10)
60
1920 Ã ffll_ref
High range (DRS=11)
80
2560 Ã ffll_ref
fdco_t_DMX3 DCO output
2
frequency
Low range (DRS=00)
â
732 Ã ffll_ref
Mid range (DRS=01)
â
1464 Ã ffll_ref
Mid-high range (DRS=10)
â
2197 Ã ffll_ref
High range (DRS=11)
â
2929 Ã ffll_ref
Jcyc_fll FLL period jitter
â
⢠fVCO = 48 MHz
⢠fVCO = 98 MHz
â
tfll_acquire FLL target frequency acquisition time
â
PLL
fvco
VCO operating frequency
48.0
Ipll
PLL operating current
⢠PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
â
2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
⢠PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
â
2 MHz, VDIV multiplier = 24)
fpll_ref PLL reference frequency range
2.0
Jcyc_pll PLL period jitter (RMS)
⢠fvco = 48 MHz
â
⢠fvco = 100 MHz
â
Typ.
â
Max.
â
â
20.97
39.0625
25
41.94
50
62.91
75
83.89
100
23.99
â
47.97
â
71.99
â
95.98
â
180
â
150
â
â
1
â
100
1060
â
600
â
â
4.0
120
â
50
â
Unit
kHz
kHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ms
MHz
µA
µA
MHz
ps
ps
Notes
2, 3
4, 5
6
7
7
8
Table continues on the next page...
K51 Sub-Family Data Sheet, Rev. 2, 4/2012.
Freescale Semiconductor, Inc.
27
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