908E626 Datasheet, PDF (27/38 Pages) Freescale Semiconductor, Inc – Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
CSA — H-Bridges Current Sense Amplification Select Bit
This read / write bit selects the current sense amplification
of the H-Bridges. Reset clears the CSA bit.
• 1 = Current sense amplification set for measuring 0.5 A.
• 0 = Current sense amplification set for measuring 2.5 A.
CLS2 : CLS0 — H-Bridge Current Limitation Selection Bits
These read / write bits select the current limitation value
according to Table 5. Reset clears the CLS2 : CLS0 bits.
Table 5. H-Bridge Current Limitation Value Selection
CLS2 CLS1 CLS0
Current Limit
0
0
0
0
0
1
No Limit
0
1
0
0
1
1
55 mA (typ)
1
0
0
260 mA (typ)
1
0
1
370 mA (typ)
1
1
0
550 mA (typ)
1
1
1
740 mA (typ)
Bits
Switchable VDD Outputs
The HVDD terminal is a switchable VDD output terminal. It
can be used for driving external circuitry that requires a V_DD
voltage. The output is enabled with bit PSON in the System
Control Register and can be switched on / off with bit
HVDDON in the Power Output Register. Low- or high-voltage
conditions (LVI / HVI) have no influence on this circuitry.
HVDD Overtemperature Protection
Overtemperature protection is enabled if the high-
temperature reset is enabled.
HVDD Overcurrent Protection
The HVDD output is protected against overcurrent. In the
event the overcurrent limit is or was reached, the output
automatically switches off and the HVDD overcurrent flag in
the System Status Register is set.
System Control Register (SYSCTL)
Register Name and Address: SYSCTL - $03
Bit7 6
5
4
3 2 1 Bit0
Read
0
0
0
0
PSON SRS1 SRS0
0
(14)
Write
Reset 0
0
0
0
0
0
0
0
Notes
15. This bit must always be set to 0.
PSON — Power Stages On Bit
This read / write bit enables the power stages (half-bridges,
LIN transmitter and HVDD output). Reset clears the PSON
bit.
• 1 = Power stages enabled.
• 0 = Power stages disabled.
SRS0 : SRS1 — LIN Slew Rate Selection Bits
These read / write bits enable the user to select the
appropriate LIN slew rate for different baud rate
configurations as shown in Table 6.
The high speed slew rates are used, for example, for
programming via the LIN and are not intended for use in the
application.
Table 6. LIN Slew Rate Selection Bits
SRS1
SRS0
LIN Slew Rate
0
0
Initial Slew Rate (20 kBaud)
0
1
Slow Slew Rate (10 kBaud)
1
0
High Speed II (8 x)
1
1
High Speed I (4 x)
System Status Register (SYSSTAT)
Register Name and Address: SYSSTAT - $0c
Bit7 6
5
4
3
2
1 Bit0
Read
Write
0
LINCL _HVDD
_OCF
0
LVF HVF _{HB_} HTF
OCF
Reset 0
0
0
0
0
0
0
0
LINCL — LIN Current Limitation Bit
This read-only bit is set if the LIN transmitter operates in
current limitation region. Due to excessive power dissipation
in the transmitter, software is advised to turn the transmitter
off immediately.
• 1 = Transmitter operating in current limitation region.
• 0 = Transmitter not operating in current limitation
region.
Analog Integrated Circuit Device Data
Freescale Semiconductor
908E626
27