MC68020RC25E Datasheet, PDF (264/306 Pages) Freescale Semiconductor, Inc – Object-Code Compatible with Earlier M68000 Microprocessors

Freescale Semiconductor, Inc.
Table 9-2. V_CC and GND Pin Assignments—
MC68EC020 PPGA (RP Suffix)
Pin Group
Address Bus
Data Bus
Internal Logic
Clock
V_CC
B7, C7
K12, M9, N9
D1, D2, E12, E13
—
GND
A1, A7, C8, D13
J13, L8, M1, M8
F11, F12, J1, J2
B1
Table 9-3. V_CC and GND Pin Assignments—
MC68EC020 PQFP (FG Suffix)
Pin Group
Address Bus
Data Bus
Internal Logic
Clock
V_CC
90
44, 57
7, 8, 70, 71
—
GND
72, 89, 100
26, 43, 58, 59
3, 20, 21, 68, 69
4
9.4 CLOCK DRIVER
The MC68020/EC020 is designed to sustain high performance while using low-cost
memory subsystems. The MC68020/EC020 requires a stable clock source that is free of
ringing and ground bounce, has sufficient rise and fall times, and meets the minimum and
maximum high and low cycle times. The individual system may require additional clocks
for peripherals with a minimum amount of clock skew. Two possible clock solutions are
provided with the MC88916 and MC74F803. Many other clock solutions can be used.
Some crystal clock drivers are capable of driving the MC68020/EC020 directly. For slower
speed designs, a simple 74F74 flip-flop meets the clocking needs of the MC68020/EC020.
Coupled with the MC88916 or MC74F803 clock generation and distribution circuit, the
MC68020/EC020 provides simple interface to lower speed memory subsystems. The
MC88916 (see Figure 9-7) and MC74F803 (see Figure 9-8) generate the clock signals
required to minimize the skew between different clocks to multiple devices such as
coprocessors, synchronous state machines, DRAM controllers, and memory subsystems.
The MC88916 clock driver can be used in doubling and synchronizing a low-frequency
clock source. The MC74F803 will provide a controlled skew output for clocking other
peripherals.
9-10
M68020 USER’S MANUAL
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