MC1322X Datasheet, PDF (26/54 Pages) Freescale Semiconductor, Inc – Advanced ZigBee™- Compliant Platform-in-Package (PiP) for the 2.4 GHz IEEE® 802.15.4 Standard

5.8 Analog-to-Digital Converter (ADC) Module
The MC1322x ADC module provides two 12-bit analog-to-digital converters (ADC_1 and ADC_2) with
eight external channels (ADC7 - ADC0) that can be multiplexed to either ADC. ADC_1 can also sample
a battery reference voltage for monitoring purposes. External pins (ADC2_VREFH, ADC2_VREFL,
ADC1_VREFH, and ADC1_VREFL) are provided for independent ADC reference voltages. The
minimum sample time is 20 µs. Figure 8 shows a block diagram of the ADC module.
Each ADC can be programmed to scan multiple selected channels on a timed basis. The primary clock to
the ADC module is the peripheral reference clock (typically 24 MHz). For the time period between scan
sequences, the primary clock is first divided by an 8-bit prescale (1-255), and the derived clock drives both
the 32-bit delay timer and the ADC sequencer. Each ADC has its own delay timer and sequencer.
Once a scan sequence has been initiated, all selected channels can be sampled. Registers are provided to
define thresholds that can be enabled for the sampled channels. A threshold can be assigned to a specific
channel and can be programmed to be a less-than or greater-than threshold. Multiple thresholds can be
assigned to a single channel. Warm-up of the analog portion of the ADC circuitry is provided for power
management, and a separate 300 kHz ADC clock must be programmed via its own divider.
The battery monitor has two (2) dedicated threshold registers to set the high and low limits of the battery
sample channel.
Sample values are stored in a 8x16-bit FIFO. The FIFO accumulates samples from both ADCs, and the
12-bit sample value and a 4-bit channel tag are saved for each sample. The FIFO is read by the CPU from
a register address.
The module can be programmed to interrupt the processor based on the timed sample activity. Sample
activity, sequencer activity, or FIFO “fullness” can all be enabled to generate an interrupt.
The ADCs can also be overridden to sample on command as opposed to sequencer, time-based activity.
C o n tro l
R e g is te rs
MCU
DATA
BUS
P re s c a le r
P e rip h e ra l
Reference Clock
3 2 -B it
Tim er
C om pare
3 2 -B it
T im e r
D iv id e r
Control
O v e rrid e
Mode
Sequencer
1
M
U
X
ADC1 Enable
FIFO
(8 x 16-Bit,
12-bit
value + 4-
bit channel
Tag)
Control
O v e rrid e
Mode
Sequencer
2
M
U
X
ADC2 Enable
300 kHz
ADC1 Mux Sel
M
ADC_1
U
X
B a tte ry
M
ADC_2
U
X
ADC2 Mux Sel
A n a lo g
Figure 8. ADC Module Block Diagram
Analog Channels
ADC0 - ADC7
MC1322x Technical Data, Rev. 1.3
26
Freescale Semiconductor