MC68HC908JB16_13 Datasheet, PDF (251/332 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
13.3.3 Reference Divider
The crystal oscillator frequency (OSCXCLK) is fed to the phase detector
through a 10-bit programmable divider module R. The divider output
(CGMRCLK) is equal to CGMXCLK divided by R and is used as the final
reference signal for the phase detector.
13.3.4 VCO Frequency Divider
The VCO output clock (CGMVCLK) is fed to the phase detector through
another 12-bit programmable divider module N. The divider output
(CGMFCLK) is equal to CGMVCLK divided by N and it is the feedback
signal for the phase detector.
13.3.5 Phase Detector
The phase detector compares the VCO feedback clock with the final
reference clock. A correction pulse is generated based on the phase
difference between the two signals. The loop filter then slightly alters the
DC voltage on the external capacitor connected to pin CGMXFC base
on the width and direction of the correction pulse.
13.3.6 Phase Detector Filter
The loop filter controls the dynamic characteristics of the PLL. The loop
filter can make fast or low corrections depending on whether the phase
detector is unlocked or stable.
13.3.7 Lock Detector
The lock detector compares the frequencies of the VCO feedback clock,
CGMFCLK, and the final reference clock, CGMRCLK. Therefore, the
speed of the lock detector is directly proportional to the final reference
clock, CGMRCLK.
MC68HC908JB16 — Rev. 1.1
Freescale Semiconductor
Clock Generator Module (CGM)
Technical Data
251