DSP56321 Datasheet, PDF (25/84 Pages) Freescale Semiconductor, Inc – 24-Bit Digital Signal Processor

AC Electrical Characteristics
Table 2-5. External Clock Operation (Continued)
No.
Characteristics
Symbol
200 MHz
Min
Max
220 MHz
Min
Max
240 MHz
Min
Max
275 MHz
Min
Max
4 EXTAL cycle time³
• With DPLL disabled
• With DPLL enabled
ET_C
5.0 ns
∞
4.55 ns
∞
4.17 ns
∞
3.64 ns
∞
5.0 ns 62.5 ns 4.55 ns 62.5 ns 4.17 ns 62.5 ns 3.64 ns 62.5 ns
7 Instruction cycle time =
I_CYC = ET_C
• With DPLL disabled
• With DPLL enabled
I_CYC
10 ns
5.0 ns
∞
1.6 µs
9.09 ns
4.55 ns
∞
1.6 µs
8.33 ns
4.17 ns
∞
1.6 µs
7.28 ns
3.64 ns
∞
1.6 µs
Notes: 1. The rise and fall time of this external clock should be 2 ns maximum.
2. Refer to Table 2-6 for a description of PDF and PDFR.
3. Measured at 50 percent of the input transition.
4. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time
required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock
frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time
requirements are met.
Note: If an externally-supplied square wave voltage source is used, disable the internal oscillator circuit after
boot-up by setting XTLD (PCTL Register bit 2 = 1—see the DSP56321 Reference Manual). The external
square wave source connects to EXTAL and XTAL is not used. Figure 2-2 shows the EXTAL input signal.
EXTAL
Midpoint
V_IHX
V_ILX ^ETH
2
ET_L
3
4
ET_C
Note: The midpoint is 0.5 (V_IHX + V_ILX).
Figure 2-2. External Input Clock Timing
2.4.3 Clock Generator (CLKGEN) and Digital PLL (DPLL)
Characteristics
Table 2-6. CLKGEN and DPLL Characteristics
Characteristics
Symbol
Predivision factor
PDF¹
Predivider output clock frequency range
Total multiplication factor²
Multiplication factor integer part
Multiplication factor numerator³
PDFR
MF
MFI¹
MFN
Multiplication factor denominator
MFD
Double clock frequency range
Phase lock-in time⁴
DDFR
DPLT
200 MHz
Min Max
1
16
16
32
5
15
5
15
0
127
1
128
160
400
6.8⁵
150⁶
220 MHz
Min Max
1
16
16
32
5
15
5
15
0
127
1
128
160
440
6.8⁵
150⁶
240 MHz
Min Max
1
16
16
32
5
15
5
15
0
127
1
128
160
480
6.8⁵
150⁶
275 MHz
Min Max
1
16
16
32
5
15
5
15
0
127
1
128
160
550
6.8⁵
150⁶
Unit
—
MHz
—
—
—
—
MHz
µs
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
2-5