MKL14Z64VLK4 Datasheet, PDF (24/47 Pages) Freescale Semiconductor, Inc – Technical Data Sheet KL14 Sub-Family

Peripheral operating requirements and behaviors
Table 11. SWD full voltage range electricals (continued)
Symbol
J1
Description
SWD_CLK frequency of operation
• Serial wire debug
Min.
0
Max.
25
J2
SWD_CLK cycle period
J3
SWD_CLK clock pulse width
• Serial wire debug
1/J1
—
20
—
J4
SWD_CLK rise and fall times
J9
SWD_DIO input data setup time to SWD_CLK rise
J10
SWD_DIO input data hold time after SWD_CLK rise
J11
SWD_CLK high to SWD_DIO data valid
J12
SWD_CLK high to SWD_DIO high-Z
—
3
10
—
0
—
—
32
5
—
SWD_CLK (input)
J2
J3
J3
J4
J4
Figure 4. Serial wire clock input timing
SWD_CLK
SWD_DIO
J11
SWD_DIO
J12
SWD_DIO
J11
SWD_DIO
J9
J10
Input data valid
Output data valid
Output data valid
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
Figure 5. Serial wire data timing
KL14 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
24
Freescale Semiconductor, Inc.