K40P81M100SF2V2 Datasheet, PDF (24/72 Pages) Freescale Semiconductor, Inc – K40 Sub-Family

Peripheral operating requirements and behaviors
TCLK (input)
J2
J3
J3
J4
J4
Figure 6. Test clock input timing
TCLK
Data inputs
Data outputs
Data outputs
Data outputs
J5
J6
Input data valid
J7
Output data valid
J8
J7
Output data valid
Figure 7. Boundary scan (JTAG) timing
K40 Sub-Family Data Sheet, Rev. 2, 4/2012.
24
Freescale Semiconductor, Inc.