68HC05P9A_1 Datasheet, PDF (24/90 Pages) Freescale Semiconductor, Inc – SPECIFICATION(General Release)

Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
3.3.2 I — Interrupt
When this bit is set, timer and external interrupts are masked (disabled). If an
interrupt occurs while this bit is set, the interrupt is latched and processed as soon
as the interrupt bit is cleared.
3.3.3 N — Negative
When set, this bit indicates that the result of the last arithmetic, logical, or data
manipulation was negative.
3.3.4 Z — Zero
When set, this bit indicates that the result of the last arithmetic, logical, or data
manipulation was zero.
3.3.5 C — Carry/Borrow
When set, this bit indicates that a carry or borrow out of the arithmetic logical unit
(ALU) occurred during the last arithmetic operation. This bit is also affected
during bit test and branch instructions and during shifts and rotates.
3.4 Stack Pointer (SP)
The stack pointer contains the address of the next free location on the stack.
During an MCU reset or the reset stack pointer (RSP) instruction, the stack
pointer is set to location $00FF. The stack pointer is then decremented as data is
pushed onto the stack and incremented as data is pulled from the stack.
When accessing memory, the seven most significant bits are permanently set to
0000011. These seven bits are appended to the six least significant register bits
to produce an address within the range of $00FF to $00C0. Subroutines and
interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the
stack pointer wraps around and loses the previously stored information. A
subroutine call occupies two locations on the stack; an interrupt uses five
locations.
12
7
0
0
0
0
0
1
1
0
SP
CENTRAL PROCESSING UNIT
MC68HC05P9A
3-2
Rev. 2.0
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