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MC68HC912DG128 Datasheet, PDF (239/452 Pages) Motorola, Inc – Microcontrollers | |||
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Freescale Semiconductor, Inc.
Enhanced Capture Timer
Timer Registers
BIT 7
6
5
4
SH37
SH26
SH15
SH04
RESET:
0
0
0
0
ICSYS â Input Control System Control Register
3
TFMOD
0
2
PACMX
0
1
BUFEN
0
BIT 0
LATQ
0
$00AB
Read: any time
Write: May be written once (SMODN=1). Writes are always permitted
when SMODN=0.
SHxy â Share Input action of Input Capture Channels x and y
0 = Normal operation
1 = The channel input âxâ causes the same action on the channel
âyâ. The port pin âxâ and the corresponding edge detector is
used to be active on the channel âyâ.
TFMOD â Timer Flag-setting Mode
Use of the TFMOD bit in the ICSYS register ($AB) in conjunction with
the use of the ICOVW register ($AA) allows a timer interrupt to be
generated after capturing two values in the capture and holding
registers instead of generating an interrupt for every capture.
By setting TFMOD in queue mode, when NOVW bit is set and the
corresponding capture and holding registers are emptied, an input
capture event will first update the related input capture register with
the main timer contents. At the next event the TCn data is transferred
to the TCnH register, The TCn is updated and the CnF interrupt flag
is set. See Figure 13-6.
In all other input capture cases the interrupt flag is set by a valid
external event on PTn.
0 = The timer flags C3FâC0F in TFLG1 ($8E) are set when a valid
input capture transition on the corresponding port pin occurs.
1 = If in queue mode (BUFEN=1 and LATQ=0), the timer flags
C3FâC0F in TFLG1 ($8E) are set only when a latch on the
corresponding holding register occurs.
If the queue mode is not engaged, the timer flags C3FâC0F are
set the same way as for TFMOD=0.
MC68HC912DG128 â Rev 3.0
Enhanced Capture Timer
For More Information On This Product,
Go to: www.freescale.com
Technical Data
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