MCF5475 Datasheet, PDF (23/30 Pages) Freescale Semiconductor, Inc – Integrated Microprocessor Electrical Characteristics

Fast Ethernet AC Timing Specifications
12 Fast Ethernet AC Timing Specifications
12.1 MII/7-WIRE Interface Timing Specs
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing
specs/constraints for the EMAC_10_100 I/O signals.
The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices. If this
interface is used with a specific transceiver device, the timing specs may be altered to match that specific transceiver.
Table 15. MII Receive Signal Timing
Num
Characteristic
M1 RXD[3:0], RXDV, RXER to RXCLK setup
M2 RXCLK to RXD[3:0], RXDV, RXER hold
M3 RXCLK pulse width high
M4 RXCLK pulse width low
Min
Max
Unit
5
—
ns
5
—
ns
35%
65%
RXCLK period
35%
65%
RXCLK period
M3
RXCLK (Input)
M1
M4
RXD[3:0] (Inputs)
RXDV,
RXER
M2
Figure 19. MII Receive Signal Timing Diagram
MCF5475 Integrated Microprocessor Electrical Characteristics, Rev. 3
Freescale Semiconductor
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