MCF52211 Datasheet, PDF (23/54 Pages) Freescale Semiconductor, Inc – ColdFire Microcontroller

MCF52211 Family Configurations
1.13 General Purpose Timer Signals
Table 13 describes the general purpose timer signals.
Table 13. GPT Signals
Signal Name
Abbreviation
Function
I/O
General Purpose Timer
GPT[3:0] Inputs to or outputs from the general purpose timer module.
I/O
Input/Output
1.14 Pulse Width Modulator Signals
Table 14 describes the PWM signals.
Table 14. PWM Signals
Signal Name
Abbreviation
Function
I/O
PWM Output Channels PWM[7:0] Pulse width modulated output for PWM channels.
O
1.15 Debug Support Signals
These signals are used as the interface to the on-chip JTAG controller and the BDM logic.
Table 15. Debug Support Signals
Signal Name
Abbreviation
Function
I/O
JTAG Enable
Test Reset
Test Clock
Test Mode Select
Test Data Input
Test Data Output
Development Serial
Clock
Breakpoint
JTAG_EN Select between debug module and JTAG signals at reset.
I
TRST This active-low signal is used to initialize the JTAG logic
I
asynchronously.
TCLK Used to synchronize the JTAG logic.
I
TMS
Used to sequence the JTAG state machine. TMS is sampled on the
I
rising edge of TCLK.
TDI
Serial input for test instructions and data. TDI is sampled on the rising I
edge of TCLK.
TDO
Serial output for test instructions and data. TDO is tri-stateable and is O
actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
DSCLK Development Serial Clock - Internally synchronized input. (The logic I
level on DSCLK is validated if it has the same value on two
consecutive rising bus clock edges.) Clocks the serial communication
port to the debug module during packet transfers. Maximum frequency
is PSTCLK/5. At the synchronized rising edge of DSCLK, the data
input on DSI is sampled and DSO changes state.
BKPT
Breakpoint - Input used to request a manual breakpoint. Assertion of I
BKPT puts the processor into a halted state after the current
instruction completes. Halt status is reflected on processor
status/debug data signals (PST[3:0] and PSTDDATA[7:0]) as the
value 0xF. If CSR[BKD] is set (disabling normal BKPT functionality),
asserting BKPT generates a debug interrupt exception in the
processor.
MCF52211 ColdFire Microcontroller, Rev. 0
Freescale Semiconductor
23