MCF51JF128 Datasheet, PDF (22/71 Pages) Freescale Semiconductor, Inc – Advance Information Temperature range (ambient): -40°C to 105°C

Clock modules
Table 13. MCG specifications (continued)
Symbol Description
Min.
f_dco
DCO output
Low range (DRS=00)
20
frequency range
640 × f_{fll_ref}
Mid range (DRS=01)
40
1280 × f_{fll_ref}
Mid-high range (DRS=10)
60
1920 × f_{fll_ref}
High range (DRS=11)
80
2560 × f_{fll_ref}
f_{dco_t_DMX3} DCO output
2
frequency
Low range (DRS=00)
—
732 × f_{fll_ref}
Mid range (DRS=01)
—
1464 × f_{fll_ref}
Mid-high range (DRS=10)
—
2197 × f_{fll_ref}
High range (DRS=11)
—
2929 × f_{fll_ref}
J_{cyc_fll} FLL period jitter
—
J_{acc_fll} FLL accumulated jitter of DCO output over a 1µs
—
time window
t_{fll_acquire} FLL target frequency acquisition time
—
PLL
f_vco
VCO operating frequency
48.0
I_pll
PLL operating current
• PLL @ 96 MHz (f_{osc_hi_1} = 8 MHz, f_{pll_ref} =
—
2 MHz, VDIV multiplier = 48)
I_pll
PLL operating current
• PLL @ 48 MHz (f_{osc_hi_1} = 8 MHz, f_{pll_ref} =
—
2 MHz, VDIV multiplier = 24)
f_{pll_ref} PLL reference frequency range
2.0
J_{cyc_pll} PLL period jitter
• f_vco = 48 MHz
—
• f_vco = 100 MHz
—
Typ.
20.97
41.94
62.91
83.89
23.99
47.97
71.99
95.98
TBD
TBD
—
—
1060
600
—
120
50
Max.
25
50
75
100
—
—
—
—
TBD
TBD
1
100
—
—
4.0
—
—
J_{acc_pll}
PLL accumulated jitter over 1µs window
• f_vco = 48 MHz
• f_vco = 100 MHz
—
1350
—
—
600
—
Table continues on the next page...
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ms
MHz
µA
µA
MHz
ps
ps
ps
ps
Notes
2, 3
4, 5
6
6
7
8
8
9, 10
9, 10
MCF51JF128 Advance Information Data Sheet, Rev. 2, 05/2011.
22
Preliminary
Freescale Semiconductor, Inc.