MCF5373_08 Datasheet, PDF (20/44 Pages) Freescale Semiconductor, Inc – ColdFire® Microprocessor

Electrical Characteristics
FB_CLK
FB_A[23:0]
FB_D[31:X]
S0
S1
S2
FB1
ADDR[23:0]
FB2
ADDR[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB6
FB7
FB_TA
Figure 7. FlexBus Write Timing
S3
FB3
5.7 SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports standard SDRAM or
double data rate (DDR) SDRAM, but it does not support both at the same time.
5.7.1 SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the memory bus clock,
when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device’s SDRAM controller is a
DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must remain supplied to the device
for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during read
cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SD_SDR_DQS signal and its usage.
Table 10. SDR Timing Specifications
Symbol
Characteristic
• Frequency of Operation¹
SD1 Clock Period²
SD3 Pulse Width High³
SD4 Pulse Width Low⁴
SD5
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Valid
SD6
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Hold
SD7 SD_SDR_DQS Output Valid⁵
SD8 ^{SD_DQS[3:0] input setup relative to SD_CLK6}
Symbol
•
t_SDCK
t_SDCKH
t_SDCKH
t_SDCHACV
Min
TBD
12.5
0.45
0.45
—
Max
Unit
80
MHz
TBD
ns
0.55
SD_CLK
0.55
SD_CLK
0.5 × SD_CLK
+ 1.0
ns
t_SDCHACI
2.0
—
ns
t_DQSOV
—
Self timed
ns
t_DQVSDCH
0.25 ×
SD_CLK
0.40 × SD_CLK
ns
MCF537x ColdFire^® Microprocessor Data Sheet, Rev. 3
20
Freescale Semiconductor