MCF53281CVM240 Datasheet, PDF (20/50 Pages) Freescale Semiconductor, Inc – MCF532x ColdFire Microprocessor Data Sheet

Electrical Characteristics
Table 8. PLL Electrical Characteristics (continued)
Num
Characteristic
Symbol
Min.
Value
Max.
Value
Unit
12 ^{Crystal capacitive load}
C_L
See crystal
spec
Discrete load capacitance for XTAL
13
C_{L_XTAL}
2*C_L –
pF
C_{S_XTAL} –
C_{PCB_XTAL7}
Discrete load capacitance for EXTAL
14
CLKOUT Period Jitter, ^{3, 4, 7, 8, 9} Measured at f_SYS Max
17
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter
18
Frequency Modulation Range Limit ^{3, 10, 11}
(f_sysMax must not be exceeded)
C_{L_EXTAL}
C_jitter
C_mod
2*C_L–-
pF
C_{S_EXTAL} –
C_{PCB_EXTAL7}
—
10
% f_sys/3
—
TBD
% f_sys/3
0.8
2.2
%f_sys/3
19 VCO Frequency. f_vco = (f_{ref *} PFD)/4
f_vco
350
540
MHz
1 _{The maximum allowable input clock frequency when booting with the PLL enabled is 24MHz. For higher input clock}
frequencies the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency.
2 _{All internal registers retain data at 0 Hz.}
3 _{This parameter is guaranteed by characterization before qualification rather than 100% tested.}
4 _{Proper PC board layout procedures must be followed to achieve specifications.}
5 _{This parameter is guaranteed by design rather than 100% tested.}
6 _{This specification is the PLL lock time only and does not include oscillator start-up time.}
7 _{CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.}
8 _{Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys.}
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the PLL circuitry via PLL V_DD, EV_DD, and V_SS and variation in crystal oscillator frequency increase
the Cjitter percentage for a given interval.
9 _{Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod.}
10 _{Modulation percentage applies over an interval of 10 μs, or equivalently the modulation rate is 100 KHz.}
11 _{Modulation range determined by hardware design.}
5.6 External Interface Timing Characteristics
Table 9 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and output delay with
respect to the rising edge of a reference clock. The reference clock is the FB_CLK output.
All other timing relationships can be derived from these values. Timings listed in Table 9
are shown in Figure 7 and Figure 8.
MCF532x ColdFire^® Microprocessor Data Sheet, Rev. 5
20
Freescale Semiconductor