MC9S08QE32_09 Datasheet, PDF (20/46 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Electrical Characteristics
Table 11. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued)
Num C
Characteristic
Symbol Min Typical¹ Max Unit
8
C
Total deviation of trimmed DCO output frequency over voltage
and temperature
Δf_{dco_t}
—
0.5
–1.0
±2 %f_dco
9
C
Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0 °C to 70 °C
Δf_{dco_t}
—
±0.5
±1 %f_dco
10 C _{FLL acquisition time}³
t_Acquire
—
—
1
ms
Long term jitter of DCO output clock (averaged over 2-ms
11 C _interval)4
C_Jitter
—
0.02
0.2 %f_dco
1 _{Data in Typical column is characterized at 3.0 V, 25 °C or is typical recommended value.}
2 _{The resulting bus clock frequency must not exceed the maximum specified bus clock frequency of the device.}
3 _{This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or}
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
4 _{Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.}
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V_DD and V_SS and variation in crystal oscillator frequency increase the C_Jitter percentage
for a given interval.
3.10 AC Characteristics
This section describes timing characteristics for each peripheral system.
3.10.1 Control Timing
Num
1
2
3
4
5
6
7
Table 12. Control Timing
C
Rating
Symbol
Bus frequency (t_cyc = 1/f_Bus)
D
D Internal low power oscillator period
V_DD ≤ 2.1V
2.1<V_DD ≤ 2.4V
V_DD > 2.4Vs
f_Bus
t_LPO
D _{External reset pulse width}²
t_extrst
D Reset low drive
t_rstdrv
D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
t_MSSU
D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes ³
t_MSH
IRQ pulse width
D
Asynchronous path² t_ILIH, t_IHIL
Synchronous path⁴
Min
DC
700
100
34 × t_cyc
500
100
100
1.5 × t_cyc
Typical¹ Max
—
10
20
25.165
—
1300
—
—
—
—
—
—
—
—
—
—
—
—
Unit
MHz
μs
ns
ns
ns
μs
ns
MC9S08QE32 Series MCU Data Sheet, Rev. 6
20
Freescale Semiconductor