908E626 Datasheet, PDF (20/38 Pages) Freescale Semiconductor, Inc – Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SS
MOSI
MISO
Read/Write, Address, Parity
R/W A4 A3 A2 A1 A0 P X
System Status Register
S7 S6 S5 S4 S3 S2 S1 S0
Data (Register write)
D7 D6 D5 D4 D3 D2 D1 D0
Data (Register read)
D7 D6 D5 D4 D3 D2 D1 D0
SPSCK
Rising edge of SPSCK
Change MISO/MOSI
Output
Falling edge of SPSCK
Sample MISO/MOSI
Input
Slave latch
register address
Slave latch
data
Figure 10. SPI Protocol
During the inactive phase of SS, the new data transfer is
prepared. The falling edge on the SS line indicates the start
of a new data transfer and puts MISO in the low-impedance
mode. The first valid data are moved to MISO with the rising
edge of SPSCK.
The MISO output changes data on a rising edge of
SPSCK. The MOSI input is sampled on a falling edge of
SPSCK. The data transfer is only valid if exactly 16 sample
clock edges are present in the active phase of SS.
After a write operation, the transmitted data is latched into
the register by the rising edge of SS. Register read data is
internally latched into the SPI at the time when the parity bit
is transferred. SS HIGH forces MISO to high impedance.
MASTER ADDRESS BYTE
A4 : A0
Contains the address of the desired register.
R/W
Contains information about a read or a write operation.
• If R/W = 1, the second byte of master contains no valid
information, slave just transmits back register data.
• If R/W = 0, the master sends data to be written in the
second byte, slave sends concurrently contents of
selected register prior to write operation, write data is
latched in the SMARTMOS register on rising edge of
SS.
Parity P
The parity bit is equal to “0” if the number of 1 bits is an
even number contained within R/ W, A4 : A0. If the number of
1 bits is odd, P equals “1”. For example, if R/ W = 1, A4 : A0 =
00001, then P equals “0.”
The parity bit is only evaluated during a write operation.
Bit X
Not used.
Master Data Byte
Table 2. Contains data to be written or no valid data during
a read operation.
908E626
20
Analog Integrated Circuit Device Data
Freescale Semiconductor