MCHC908GR8CFAE Datasheet, PDF (192/408 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Freescale Semiconductor, Inc.
Monitor ROM (MON)
The monitor code has been updated from previous versions to allow
enabling the PLL to generate the internal clock, provided the reset vector
is blank, when the device is being clocked by a low-frequency crystal.
This addition, which is enabled when IRQ is held low out of rest, is
intended to support serial communication/ programming at 9600 baud in
monitor mode by stepping up the external frequency (assumed to be
32.768 kHz) by a fixed amount to generate the desired internal
frequency (2.4576 MHz). Since this feature is enabled only when IRQ is
held low out of reset, it cannot be used when the reset vector is not blank
because entry into monitor mode in this case requires V_TST on IRQ.
15.4.1 Entering Monitor Mode
Table 15-1 shows the pin conditions for entering monitor mode. As
specified in the table, monitor mode may be entered after a power-on
reset (POR) and will allow communication at 9600 baud provided one of
the following sets of conditions is met:
1. If $FFFE and $FFFF contain values not cared:
– The external clock is 9.8304 MHz
– IRQ = V_TST (PLL off)
2. If $FFFE and $FFFF contain $FF, blank state:
– The external clock is 9.8304 MHz
– IRQ = V_DD (this can be implemented through the internal IRQ
pullup; PLL off)
3. If $FFFE and $FFFF contain $FF, blank state:
– The external clock is 32.768 kHz (crystal)
– IRQ = V_SS (this setting initiates the PLL to boost the external
32.768 kHz to an internal bus frequency of 2.4576 MHz)
Technical Data
192
MC68HC908GR8 — Rev 4.0
Monitor ROM (MON)
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