908E625_07 Datasheet, PDF (19/48 Pages) Freescale Semiconductor, Inc – Integrated Quad Half H-Bridge with Power Supply, Embedded MCU, and LIN Serial Communication

SERIAL SPI INTERFACE
The SPI creates the communication link between the
microcontroller and the 908E625.
The interface consists of four pins. See Figure 9:
• SS—Slave Select
• MOSI—Master-Out Slave-In
SS
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
• MISO—Master-In Slave-Out
• SPSCK—Serial Clock
A complete data transfer via the SPI consists of 2 bytes.
The master sends address and data, slave system status,
and data of the selected address.
MOSI
Read/Write, Address, Parity
R/W A4 A3 A2 A1 A0 P X
Data (Register write)
D7 D6 D5 D4 D3 D2 D1 D0
MISO
System Status Register
S7 S6 S5 S4 S3 S2 S1 S0
Data (Register read)
D7 D6 D5 D4 D3 D2 D1 D0
SPSCK
Rising edge of SPSCK
Change MISO/MOSI
Output
Falling edge of SPSCK
Sample MISO/MOSI
Input
Slave latch
register address
Slave latch
data
Figure 9. SPI Protocol
During the inactive phase of SS, the new data transfer is
prepared. The falling edge on the SS line indicates the start
of a new data transfer and puts MISO in the low-impedance
mode. The first valid data are moved to MISO with the rising
edge of SPSCK.
selected register prior to write operation, write data is
latched in the SMARTMOS™ register on rising edge of
SS.
PARITY P
The MISO output changes data on a rising edge of
SPSCK. The MOSI input is sampled on a falling edge of
SPSCK. The data transfer is only valid if exactly 16 sample
clock edges are present in the active phase of SS.
The parity bit is equal to 0 if the number of 1 bits is an even
number contained within R/W, A4:A0. If the number of 1 bits
is odd, P equals 1. For example, if R/W = 1, A4:A0 = 00001,
then P equals 0.
After a write operation, the transmitted data is latched into
the register by the rising edge of SS. Register read data is
internally latched into the SPI at the time when the parity bit
is transferred. SS HIGH forces MISO to high impedance.
The parity bit is only evaluated during a write operation.
BIT X
Not used.
A4 : A0
Contains the address of the desired register.
R/W
Contains information about a read or a write operation.
• If R/W = 1, the second byte of master contains no valid
information, slave just transmits back register data.
• If R/W = 0, the master sends data to be written in the
second byte, slave sends concurrently contents of
MASTER DATA BYTE
Contains data to be written or no valid data during a read
operation.
SLAVE STATUS BYTE
Contains the contents of the System Status Register ($0c)
independent of whether it is a write or read operation or which
register was selected.
Analog Integrated Circuit Device Data
Freescale Semiconductor
908E625
19