16XSD200 Datasheet, PDF (19/60 Pages) Freescale Semiconductor, Inc – Dual 16 mOhm High Side Switch

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Unless specified otherwise: 8.0 V  V_PWR  36 V, 3.0 V  V_DD  5.5 V, -40 C  T_A  125 C, GND = 0 V. Typical values are
average values evaluated under nominal conditions T_A = 25 °C,V_PWR = 28 V & V_DD = 5.0 V, unless specified otherwise.
Parameter
Symbol
Min
Typ
Max
Unit
GND PIN TEMPERATURE SENSING FUNCTION
Thermal Prewarning Detection Threshold⁽³⁸⁾
T_OTWAR
Temperature Sensing output voltage @ T_A = 25 °C (470  < R_CSNS < 10 k
Gain Temperature Sensing output @ T_A = 25 °C (470  < R_CSNS < 10 k⁽³⁸⁾
Temperature Sensing Error, range [-40 °C, 150 °C], default⁽³⁸⁾
T_FEED
DT_FEED
T_{FEED_ERROR}
Temperature Sensing Error, [-40 °C, 150 °C] after 1 point calibration @ 25 °C⁽³⁸⁾ T_{FEED_ERROR}
_CAL
SPI INTERFACE ELECTRICAL CHARACTERISTICS⁽³⁹⁾
110
918
10.7
-15
-5.0
125
1078
11.1
–
–
140
1238
11.5
+15
+5.0
°C
mV
mV/°C
°C
°C
Maximum Operating Frequency of the Serial Peripheral Interface (SPI)⁽⁴⁵⁾
f _SPI
–
–
8.0
MHz
Required Low-state Duration for reset RSTB ⁽⁴⁰⁾
t _WRSTB
10
–
–
s
Required duration from the Rising to the Falling Edge of CSB (Required Setup
Time)⁽⁴¹⁾
t _CSB
1.0
–
–
s
Rising Edge of RSTB to Falling Edge of CSB (Required Setup Time)⁽⁴¹⁾
Falling Edge of CSB to Rising Edge of SCLK (Required Setup Time)⁽⁴¹⁾
Falling Edge of SCLK to Rising Edge of CSB (Required Setup lag Time)⁽⁴¹⁾
t _ENBL
5.0
–
t _LEAD
500
–
t _LAG
60
–
Required High State Duration of SCLK (Required Setup Time)⁽⁴¹⁾
Required Low State Duration of SCLK (Required Setup Time)⁽⁴¹⁾
SI to Falling Edge of SCLK (Required Setup Time)⁽⁴²⁾
t _WSCLKh
50
–
t _WSCLKl
50
–
t _{SI (SU)}
15
–
Falling Edge of SCLK to SI (Required hold Time of the SI signal)⁽⁴²⁾
t _{SI (H)}
30
–
SO Rise Time
C_L = 80 pF
t _RSO
–
–
–
s
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
20
ns
SO Fall Time
C_L = 80 pF
t _FSO
–
–
20
ns
SI, CSB, SCLK, Max. Rise Time allowing operation at f_SPI = 8.0 MHz⁽⁴²⁾
t _RSI
–
–
11
ns
SI, CSB, SCLK, Max. Fall Time allowing operation at f_SPI = 8.0 MHz⁽⁴²⁾
t _FSI
–
–
11
ns
Time from Rising Edge of SCLK to reach a valid level at the SO pin⁽⁴³⁾
t_VALID
–
–
44
ns
Time from Falling Edge of CSB to reach low-impedance on SO (access time)⁽⁴⁴⁾
t _SOEN
–
–
30
ns
Notes:
38. Values were obtained by lab. characterization
39. Parameters guaranteed by design. It is recommended to tie unused SPI-pins to GND by resistors 1.0 k <R <10 k
40. RSTB low duration is defined as the minimum time required to switch off the channel when previously put ON in SPI mode (direct inputs
inactive).
41. Minimum setup time required for the device is the minimum required time that the microcontroller must wait or remain in a given state.
42. Rise and Fall time of incoming SI, CSB, and SCLK signals.
43. Time required for output data to be available for use at SO, measured with a 1.0 kseries resistorconnected CSB.
44. Time required for output data to be terminated at SO measured with a 1.0 kseries resistorconnected CSB.
45. For clock frequencies > 4.0 MHz, series resistors on the SPI pins should preferably be removed. Otherwise, 470 pF (V_MAX. > 40 V)
ceramic speed-up capacitors in parallel with the >8.0 k input resistors are required on pins SCLK, SI, SO, CS
Analog Integrated Circuit Device Data
Freescale Semiconductor
16XSD200
19