33730_12 Datasheet, PDF (18/28 Pages) Freescale Semiconductor, Inc – Switch Mode Power Supply with Multiple Linear Regulators

FUNCTIONAL DEVICE OPERATION
OPERATION DESCRIPTION
PROGRAMMING LINEAR REGULATOR OUTPUT
VOLTAGE
The output voltage of the VDD3, VDDL and VKAM outputs
can be externally programmed by placing logic levels on the
programming pins P1, P2, and P3 (see Table 7). This
extends the application flexibility of the IC without having to
use an external resistor divider, thus improving the regulator
accuracy over the whole temperature range, and reducing
the component count.
The logic level of the programming pin (Px) can be
selected by tying the pin to ground (logic level "0") or to
protected battery voltage (logic level "1"). Programming pins
must never be left floating, they must be tied to either ground
or protected battery voltage.
The programming information is read and latched with the
500 μs delay after the power is applied to the IC.
Table 7. Programming VDD3, VDDL, VKAM Output
Voltage
P1
P2
P3
V_DD3
V_DDL
V_KAM
High
High
High
3.3 V
2.6 V
2.6 V
High
High
Low
3.3 V
3.3 V
3.3 V
High
Low
High
3.3 V
1.5 V
1.0 V
High
Low
Low
3.3 V
3.3 V
1.0 V
Low
High
High 3.3 V Standby
3.3 V
1.0 V
Low
High
Low
2.0 V
3.15 V
5.0 V
Low
Low
High 2.6 V Standby 3.3 V
1.0 V
Low
Low
Low 2.6 V Standby 3.3 V
1.5 V
The Programming Pins can be tied high, to protected battery
voltage, or low, to ground.
LOW BATTERY OPERATION
When the battery voltage falls below the specified
minimum value, the 33730 switching regulator will enter a
100% duty cycle mode of operation and its output voltage
V_DDH will follow the decreasing battery voltage. If the battery
voltage continues to fall, the V_DDH voltage reaches its reset
threshold level, and the RSTH signal will be pulled low, but
the other linear regulators will continue to operate, and their
monitoring signals stay high as long as the VDDH provides
sufficient headroom for the regulators to stay in their
regulation limits (see Figure 6 and Figure 7). If the battery
voltage continues to fall, the linear regulators would not have
sufficient headroom to stay in regulation, and their resets
would be asserted (RSTL, RST3, or both would be pulled
low). At that moment the power down sequence would be
engaged.
The V_KAM standby regulator will operate down to (V_{KAM and}
V_{KAM_DO)} and V_KAM-DO at the KA_VBAT pin.
POWER SEQUENCING (VDDH, VDD3, VDDL)
V_DDH, V_DD3, and V_DDL are power sequenced by means of
internal pull-down FETs. During the power up sequence,
V_DD3 and V_DDL will follow V_DDH.
33730
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During the power down sequence the VDD3 and VDDL
outputs will be pulled down by the internal pull-down power
FETs, and V_DDH will be shut off with a defined delay (~100 μs
typ.).
In order to engage the power down sequence, the
following conditions have to be met:
(VIGN . REGON) + UVLO = Power Down
The VDD3 output is not power sequenced when used as a
standby regulator.
SENSOR SUPPLIES (VREF1, VREF2)
There are two sensor supplies, VREF1 and VREF2,
integrated into the IC. They are internally connected to V_DDH
through power MOSFETs which protect against short to
battery and short to ground conditions.
Severe fault conditions on the VREF1 and VREF2 outputs,
like shorts to either ground or battery, will not disrupt the
operation of the main regulator V_DDH, or cause assertion of
any Reset signal.
IMPORTANT NOTE:
The VREF outputs MUST be externally protected against
transient voltage events with slew rates faster than
2.0 V/μs, otherwise damage to the part may occur. A
practical and inexpensive solution consists of using a series
RC network connected from the VREF output to ground (see
Figures 8 and 9 for typical component values). Other means,
such as a single electrolytic capacitor with its capacitance
value C > 10 μF, may be also used.
PROTECTION FET DRIVE (PFD)
The Protection FET Drive circuit allows using an optional
N-channel protection MOSFET (instead of a standard
reverse protection diode) to protect against a reverse battery
voltage condition. This approach improves the operating
capabilities at very low battery voltages.
An internal charge pump is used to enhance the
Protection FET gate during nominal and low battery
conditions. The charge pump will be enabled at the startup
voltage. When the battery voltage gets sufficiently high, the
Protection FET is turned off and the integrated circuit power
input (VBAT pins) are supplied through the body diode of the
Protection FET.
Use of the Protection FET is not necessary in systems
already using a protection diode, relay or when no reverse
battery protection is required.
CONTROL INPUT (VIGN)
The VIGN pin is used as a control input to the IC. The
regulation circuits will function and draw current from V_BAT
when V_IGN is high (active) or when the REGON pin is high.
The VIGN pin has a V_IHN-IH power-up threshold V_IGN-IL typical
power-down threshold) and V_IGN-HYS (minimum) of
hysteresis. V_IGN is designed to operate up to max V_BAT
battery while providing reverse battery and max V_BAT load
dump protection.
Analog Integrated Circuit Device Data
Freescale Semiconductor