MC9S12XEQ512CAG Datasheet, PDF (173/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.100 Port L Routing Register (PTLRR)
Address 0x0377
R
W
Reset
7
PTLRR7
0
1. Read: Anytime.
Write: Anytime.
6
5
4
3
2
0
0
PTLRR6
PTLRR5
PTLRR4
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-98. Port L Routing Register (PTLRR)
Access: User read/write⁽¹⁾
1
0
0
0
0
0
This register configures the re-routing of SCI7, SCI6, SCI5, and SCI4 on alternative ports.
Table 2-95. Port L Routing Summary
Module
PTLRR
7654
SCI7
SCI6
SCI5
SCI4
0xxx
1xxx
x0xx
x1xx
xx0x
xx1x
xxx0
xxx1
Related Pins
TXD
PH3
PL7
PH1
PL5
PH7
PL3
PH5
PL1
RXD
PH2
PL6
PH0
PL4
PH6
PL2
PH4
PL0
2.3.101 Port F Data Register (PTF)
Address 0x0378
R
W
Altern.
Function
Reset
7
PTF7
(TXD3)
0
1. Read: Anytime.
Write: Anytime.
6
PTFT6
5
PTF5
4
PTF4
3
PTF3
2
PTF2
(RXD3)
0
(SCL0)
(SDA0)
(CS3)
(CS2)
0
0
0
0
Figure 2-99. Port F Data Register (PTF)
Access: User read/write⁽¹⁾
1
0
PTF1
PTF0
(CS1)
0
(CS0)
0
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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